Reset Port Description - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

Reset pins other than the following are for debugging purposes only:

  • tx_serdes_reset[5:0]
  • rx_serdes_reset[5:0]
  • tx_core_reset
  • rx_core_reset

Register bits other than the following are for debugging purposes only:

  • soft_tx_core_reset field of GLOBAL_CONTROL_REG_TX register
  • soft_rx_core_reset field of GLOBAL_CONTROL_REG_RX register
  • c<N>_soft_tx_serdes_reset field of C<N>_PORT_CONTROL_REG_TX register
  • c<N>_soft_rx_serdes_reset field of C<N>_PORT_CONTROL_REG_RX register
  • c<N>_soft_tx_mac_channel_flush field of C<N>_CHANNEL_CONTROL_REG_TX register
  • c<N>_soft_rx_mac_channel_flush field of C<N>_CHANNEL_CONTROL_REG_RX register

Resets other than the above should not be asserted by the user logic.

Table 1. Reset Port Description
DCMAC Subsystem Reset Pin Associated Register Name Associated Register Field Description
tx_core_reset GLOBAL_CONTROL_REG_TX soft_tx_core_reset TX MAC core reset. Asserting the reset resets the time-sliced MAC TX datapath, including:

TX AXI4-Stream interface

TX MAC interface (MAC I/F)
rx_core_reset GLOBAL_CONTROL_REG_RX soft_rx_core_reset RX MAC core reset. Asserting the reset resets the time-sliced MAC RX datapath, including:

RX AXI4-Stream interface

RX MAC interface (MAC I/F)
tx_serdes_reset[5:0] C<N>_PORT_CONTROL_REG_TX c<N>_soft_tx_serdes_reset Resets the TX SerDes (GT) interface for the corresponding port. This reset does not reset the core logic or AXI4-Stream interface, but does reset the statistics or status registers related to the TX PHY, and TX flex interface.
rx_serdes_reset[5:0] C<N>_PORT_CONTROL_REG_RX c<N>_soft_rx_serdes_reset Resets the RX SerDes (GT) interface for the corresponding port. This reset does not reset the core logic or AXI4-Stream interface, but does reset the statistics or status registers related to the RX PHY, and RX flex interface.
N/A C<N>_CHANNEL_CONTROL_REG_TX c<N>_soft_tx_mac_channel_flush Clears the state of the corresponding channel in the transmit time-sliced MAC.
N/A C<N>_CHANNEL_CONTROL_REG_RX c<N>_soft_rx_mac_channel_flush Clears the state of the corresponding channel in the receive time-sliced MAC.
apb3_preset N/A N/A Resets the AXI4-Lite port logic, status, and statistics registers.