Revision History - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The following table shows the revision history for this document.

Section Revision Summary
11/08/2023 Version 2.3
Transceiver (SerDes) Modes Updated Tranceiver GT Quad Operating Modes
Customizing and Generating the Subsystem Updated DCMAC Supported Configuration in Vivado IDE
DCMAC Configuration Tab Updated Screenshots
08/08/2023 Version 2.2
DCMAC FEC Only Configuration Example Design Added the topic.
Document title Changed the title to Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem.
04/12/2023 Version 2.1
Pause Operation Added the section
Entire document
  • Added updates related to 112G serial lane rate
  • General updates
01/27/2023 Version 2.1
Simulation Speed Up Added AMD Vivado™ Simulator.
Entire document General updates.
09/05/2022 Version 2.0
Initial release N/A