Simulation Speed Up - 2.3 English

Simulation can take a long time to complete because of the time required to complete the core alignment. A `define SIM_SPEED_UP is available to improve simulation time by reducing the PCS lane alignment marker (AM) spacing to speed up the time the IP takes to achieve alignment. Setting `define SIM_SPEED_UP changes the following input ports in the example design top module.

• ctl_tx_custom_vl_length_minus1 and ctl_rx_custom_vl_length_minus1 from 16'h3FFF to 16'h00FF for 6x100 CAUI-4, 6x100 100GAUI-4, and 6x100GE 100GAUI-2 configurations.
• ctl_tx_custom_vl_length_minus1 and ctl_rx_custom_vl_length_minus1 from 16'h1000 to 16'h0100 for 3x200 200GAUI-8 and 3x200GE 200GAUI-4 configurations.
• ctl_tx_custom_vl_length_minus1 and ctl_rx_custom_vl_length_minus1 from 16'h2000 to 16'h0100 for 1x400 400GAUI-16 and 1x400GE 400GAUI-8 configurations. For 1x400G configurations, C0_CTL_RX/TX_USE_CUSTOM_VL_LENGTH_MINUS1, C1_CTL_RX/TX_USE_CUSTOM_VL_LENGTH_MINUS1, C2_CTL_RX/TX_USE_CUSTOM_VL_LENGTH_MINUS1 and C3_CTL_RX/TX_USE_CUSTOM_VL_LENGTH_MINUS1 need to be set to 16'h0100 for the SIM_SPEED_UP option.

The SIM_SPEED_UP option can be used for simulation when in serial loopback or if the AM spacing can be reduced at both endpoints. This option is compatible with the example design simulation which uses serial loopback.

Note the following:

• Altering the value of ctl_tx_custom_vl_length_minus1 and ctl_rx_custom_vl_length_minus1 from the default value will violate the IEEE 802.3 spec.
• Decreasing the AM spacing will result in less than DCMAC bandwidth being available on the link. This change can be made only in simulation. For a design to work in hardware, the default values must be used.
• Full rate simulation without the SIM_SPEED_UP option should still be run. SIM_SPEED_UP is available only when running RTL simulations. The option is not available for post-synthesis or post-implementation simulations.