This document describes the function and operation of the AMD Versal adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC Subsystem), including how to design, customize, and implement the DCMAC Subsystem.
The DCMAC Subsystem handles all protocol-related functions of an Ethernet MAC, PCS, and FEC, including handshaking, synchronizing, and error checking. It also provides a segmented AXI4-Stream interface for packet data and an AXI4-Lite interface for statistics and management.
The subsystem can provide up to six independent Ethernet ports and is designed for flexible use in many different applications. To reduce latency, the datapath does not perform any buffering other than the pipelining to perform the required operations. Received data is passed directly to the user interface in a cut-through manner, enabling the flexibility to implement any required buffering scheme. Similarly, the transmit path consists of minimal pipeline and buffering to provide reliable cut-through operation.
The DCMAC Subsystem can be configured to include forward error correction (FEC). The subsystem also provides a 40-channel 600 Gbps time-sliced MAC with flexible user-defined bandwidth allocation granularity.
The subsystem can be configured in a mode that provides the user logic with access to the 40-channel MAC using a channelized, segmented AXI4-Stream interface on one side and a channelized MAC interface (MAC I/F) on the other side. In the operation mode, the subsystem also provides the user logic with access to the PCS and/or FEC through the flex interface (FLEX I/F) on one side and the SerDes interface on the other side.
The following table lists the hard IP data rates, FEC types, and configurations. For AMD Vivado™ AMD LogiCORE™ enabled configurations, see Table 1.
| Data Rates | Datapath Functions | Integrated PCS Options |
|---|---|---|
| 1 × 400GE | MAC+PCS, PCS-only |
IEEE 802.3 CL119 RS(544,514) "KP4" FEC |
| 3 × 200GE | IEEE 802.3 CL119 RS(544,514) "KP4" FEC | |
| 6 × 100GE | No FEC, IEEE 802.3 CL91 RS(528,514) "KR4" FEC, IEEE 802.3 CL91 RS(544,514) "KP4" FEC, IEEE P802.3ck CL161 RS(544,514) "Interleaved" FEC | |
| Combinations of 100, 200, 400 (totaling up to 600 Gbps) | As per above, based on the port data rate | |
| 40 user-configurable channels (totaling up to 600 Gbps) | MAC-only | As per above (and below), PCS-only and FEC-only are available and independently selected. |
| 3 x 100GE Wide AXI-S 1 | MAC+PCS | No FEC, IEEE 802.3 CL91 RS(528,514) "KR4" FEC, IEEE 802.3 CL91 RS(544,514) "KP4" FEC, IEEE 802.3 CL161 RS(544,514) "Interleaved" FEC |
| 4 x 100GE Wide FLEX I/F 2 | PCS-only |
No FEC, IEEE 802.3 CL91 RS(528,514) "KR4" FEC, IEEE 802.3 CL91 RS(544,514) "KP4" FEC, IEEE 802.3 CL161 RS(544,514) "Interleaved" FEC |
| 6 × 128GFC | FEC-only (with deskew and 257b transcoding) |
RS(528, 514) FEC as per Fibre Channel standard |
| 4 x 128GFC Wide FLEX I/F 2 | FEC-only (with deskew and 257b transcoding) |
RS(528, 514) FEC as per Fibre Channel standard |
| 6 × 112G | FEC-only | IEEE 802.3 CL91 RS(528,514) "KR4" FEC, IEEE 802.3 CL91 RS(544,514) "KP4" FEC |
| 12 × 56.42G | FEC-only | IEEE 802.3cd CL134 RS(544,514) FEC |
| 1 × 424.8GE (Overclocked 400GE) 3 | Same as 1 × 400GE | Same as 1 × 400GE |
| 3 × 212.4GE (Overclocked 200GE) 3 | Same as 3 × 200GE | Same as 3 × 200GE |
| 6 × 106.2GE (Overclocked 100GE) 3 | Same as 6 × 100GE | Same as 6 × 100GE |
| 1 × 400G FlexO | FEC-only (with deskew) |
RS(544, 514) FEC as per G.709.1/Y.1331.1 |
| 3 × 200G FlexO | ||
| 6 × 100G FlexO | ||
| 6 x 64GFC |
FEC-only (requires additional programmable logic) |
CL91 RS(544,514) “KP4” FEC |
| 12 x 64GFC 4 |
FEC-only (requires additional programmable logic) |
CL91 RS(544,514) “KP4” FEC |
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For more information on performance capabilities of DCMAC, see Maximum Performance for DCMAC Designs table in Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959).