System Clocks - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The abp3_clk signal is a mandatory clock which must be present and stable in all modes of operation. It is used for internal configuration and synchronization functions in addition to its use as a clock for the processor interface.