Timestamp Ports - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID: PG369
Release Date: 2023-11-08
Version: 2.3 English

Table 1. Timestamp Status Interface: TX Direction
Port Name	Clock Domain	I/O	Description
tx_ptp_tstamp_port_id[2:0]	tx_axi_clk	O	Port number of TX PTP tag/timestamp
tx_ptp_tstamp_tag_0[7:0]	tx_axi_clk	O	TX timestamp tag value 0. This should match the tag value provided on input (on TX AXI or flex interface).
tx_ptp_tstamp_tag_1[7:0]	tx_axi_clk	O	TX timestamp tag value 1. This should match the tag value provided on input (on TX AXI or flex interface).
tx_ptp_tstamp_tag_2[7:0]	tx_axi_clk	O	TX timestamp tag value 2. This should match the tag value provided on input (on TX AXI or flex interface)
tx_ptp_tstamp_valid[2:0]	tx_axi_clk	O	TX PTP timestamp is valid. Up to three timestamps can be valid (one bit per timestamp). Also qualifies tags.
tx_ptp_tstamp_0[31:0]	tx_axi_clk	O	TX PTP timestamp value 0. Note: Upper bits are dropped.
tx_ptp_tstamp_1[31:0]	tx_axi_clk	O	TX PTP timestamp value 1. Note: Upper bits are dropped.
tx_ptp_tstamp_2[31:0]	tx_axi_clk	O	TX PTP timestamp value 2. Note: Upper bits are dropped.

Note: In the following tables, <N> = port number 0-5.

Table 2. Timer Control Interface: TX Direction
Port Name	Clock Domain	I/O	Description
c<N>_tx_ptp_st_adjust_vld	ts_clk[<N>]	I	A transition on this signal specifies the System Timer Adjust is valid.
c<N>_tx_ptp_st_adjust_type[1:0]	ts_clk[<N>]	I	Specifies the desired System Timer Adjustment Type. 2'h0: Adjust system timer; signed, in units of 2^–8 ns (upper 14 bits ignored). Warning, no overflow protection is done. 2'h1: Set the automatic increment value; ctl_ptp_st_adjust value is unsigned, in units of 2^–8 ns (upper 22 bits ignored). This also clears any existing increment value below 2^–8 ns (previously set by default or through adjustments). Increments every cycle. Nominal values - non-KP4: 1.551515 ns; KP4: 1.50588235 ns). 2'h2: Adjust automatic increment value; signed, in units of 2^–40 ns.
c<N>_tx_ptp_st_adjust[31:0]	ts_clk[<N>]	I	Specifies System Timer Adjust value.
c<N>_tx_ptp_st_overwrite	ts_clk[<N>]	I	System Timer Overwrite. When asserted, the internal system timer value is overwritten with tx_ptp_systemtimer.
c<N>_tx_ptp_st_sync	ts_clk[<N>]	I	System Timer Sync. The transition edge (High to Low, or Low to High) indicates when the tx_ptp_systemtimer value is valid.
c<N>_tx_ptp_systemtimer[54:0]	ts_clk[<N>]	I	System timer input in units of 2^–8 ns (unsigned). This field maps to bits[62:8] of the correction field format in IEEE 1588-2008 (with the bottom eight bits set to 0).

Table 3. Timer Status Interface: TX Direction
Port Name	Clock Domain	I/O	Description
c<N>_tx_ptp_st_sync_out	tx_serdes_clk[<N>]	O	TX path 1588 System Timer interval sync output signal. Transition indicates when tx_ptp_systemtimer_out is valid. Note: Due to internal retiming stages, tx_ptp_systemtimer_out transitions up to four ts_clk[<N>] cycles after tx_ptp_st_sync_out.
c<N>_tx_ptp_systemtimer_out[31:0]	ts_clk[>N>]	O	Port for sampling the PTP System Timer (TOD). Upper bits omitted to reduce pin count.
c<N>_tx_ptp_st_sample_edge_out	ts_clk[>N>]	O	Indicator of the system timer sampling edge.

Table 4. Timer Control Interface: RX Direction
Port Name	Clock Domain	I/O	Description
c<N>_rx_ptp_st_adjust_vld	ts_clk[<N>]	I	Specifies the System Timer Adjust is valid.
c<N>_rx_ptp_st_adjust_type[1:0]	ts_clk[<N>]	I	Specifies the desired System Timer Adjustment Type. 0: Adjust system timer; signed, in units of 2^–8 ns (upper 14 bits ignored). Warning: no overflow protection is done. 1: Set the automatic increment value; ctl_ptp_st_adjust value is unsigned, in units of 2^–8 ns (upper 22 bits ignored). This also clears any existing increment value below 2^–8 ns (previously set by default or through adjustments). Increments every cycle. Nominal values – non-KP4: 1.551515 ns; KP4: 1.50588235 ns). 2: Adjust automatic increment value; signed, in units of 2^–40 ns.
c<N>_rx_ptp_st_adjust[31:0]	ts_clk[<N>]	I	Specifies System Timer Adjust value.
c<N>_rx_ptp_st_overwrite	ts_clk[<N>]	I	System Timer Overwrite. When asserted, the internal system timer value is overwritten with tx_ptp_systemtimer.
c<N>_rx_ptp_st_sync	ts_clk[<N>]	I	System Timer Sync. The transition edge (High to Low, or Low to High) indicates when the rx_ptp_systemtimer value is valid.
c<N>_rx_ptp_systemtimer[54:0]	ts_clk[<N>]	I	System timer input in units of 2^–8 ns (unsigned). This field maps to Bits[62:8] of the correction field format in IEEE 1588-2008 (with the bottom eight bits set to 0).

Table 5. Timer Status Interface: RX Direction
Port Name	Clock Domain	I/O	Description
c<N>_rx_ptp_st_sync_out	rx_serdes_clk[<N>]	O	RX path 1588 System Timer interval sync output signal. Transition indicates when rx_ptp_systemtimer_out is valid. Note: Due to internal retiming stages, rx_ptp_systemtimer_out transitions up to four ts_clk[<N>] cycles after rx_ptp_st_sync_out.
c<N>_rx_ptp_systemtimer_out[31:0]	ts_clk[<N>]	O	Port for sampling the PTP System Timer (TOD). Upper bits omitted to reduce pin count.
c<N>_rx_ptp_st_sample_edge_out	ts_clk[<N>]	O	Indicator of the system timer sampling edge.