Transceiver Clocking Modes - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The GT Quad interface is clocked by rx_alt_serdes_clk[0] through rx_alt_serdes_clk[5] in the DCMAC Subsystem RX direction and by tx_alt_serdes_clk[0] through tx_alt_serdes_clk[5] in the DCMAC Subsystem TX direction. The rx_serdes_clk[N] connects to a GT Quad transceiver generated clock whose frequency is twice the frequency of rx_alt_serdes_clk[N]. Similarly, the tx_serdes_clk[N] connects to a GT Quad transceiver generated clock whose frequency is twice that of tx_alt_serdes_clk[N].