Transceiver (SerDes) Modes - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)

Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

The DCMAC Subsystem is capable of interfacing with the AMD Versal™ GTY/GTYP and GTM transceivers through the programmable logic region. Each GT Quad lane has a dedicated transceiver interface on the DCMAC Subsystem.

The DCMAC Subsystem has PCS/PMA lane logic functions including bit muxing, gearbox, scrambling, lane alignment, and lane deskew. For this reason, the transceivers connected to the DCMAC Subsystem must be configured to operate in RAW mode. The default transceiver lane interface configuration is 80b RAW interface for 26.5625 Gbps lane logic.

For multi-lane PMD lane data rates of 200GE or 400GE with 100 Gbps lane rate, the DCMAC Subsystem GT Quad interface can support per-lane GT Quad recovered clocks in the RX direction. This option reduces transceiver latency and improves 1588 timestamping accuracy at the cost of requiring per-lane FPGA clocking resources.

For designs in which it is preferred to reduce the clocking resources consumed by the DCMAC Subsystem link, the IP also supports having the transceivers configured with per-lane deskew buffering enabled, allowing all RX PMD lanes to share a common master lane clock.

The following table shows a list of DCMAC Subsystem-supported interface options for GT transceivers including the associated line rates, GT datapath width, and clock frequency.

Table 1. Transceiver GT Quad Operating Modes
Operating Mode RS(528,514) RS(544,514) GT Lane Line Rate (Gbps) GTY / GTM NRZ / PAM4 GT Interface Data Width (Bits) GT Interface Clock (MHz) PCS Lane Logic Internal Clock (MHz)
100GE CAUI-4 25.78125 Both NRZ 80 322.2656 644.5313
100GE 100GAUI-4 26.5625 Both NRZ 80 332.03125 664.0625
100GE 100GAUI-2 53.125 GTM PAM4 160 332.03125 664.0625
100GE 100GAUI-1 106.25 GTM PAM4 320 332.03125 664.0625
100G FlexO FOIC 1.1-RS 111.8 GTM PAM4 320 349.4061 698.8092
100G FlexO FOIC 1.2-RS 55.9 GTM PAM4 160 349.4061 698.8092
100G FlexO FOIC1.4-RS 27.95 Both NRZ 80 349.4061 698.8092
100GE (Overclocking) 100GAUI-4 28.21 Both NRZ 80 352.625 705.25
100GE (Overclocking) 100GAUI-2 56.42 GTM PAM4 160 352.625 705.25
100GE (Overclocking) 100GAUI-1 112 GTM PAM4 320 350 700
128GFC 4-lane 28.05 Both NRZ 80 350.625 701.25
200GE 200GAUI-8 26.5625 Both NRZ 80 332.03125 664.0625
200GE 200GAUI-4 53.125 GTM PAM4 160 332.03125 664.0625
200GE 200GAUI-2 106.25 GTM PAM4 320 332.03125 664.0625
200G FlexO FOIC 2.2-RS 111.8 GTM PAM4 320 349.4061 698.8092
200G FlexO FOIC2.4-RS 55.9 GTM PAM4 160 349.4061 698.8092
200GE (Overclocking) 200GAUI-4 56.42 GTM PAM4 160 352.625 705.25
200GE (Overclocking) 200GAUI-2 112 GTM PAM4 320 350 700
400GE 400GAUI-16 26.5625 Both NRZ 80 332.03125 664.0625
400GE 400GAUI-8 53.125 GTM PAM4 160 332.03125 664.0625
400GE 400GAUI-4 106.25 GTM PAM4 320 332.03125 664.0625
400G FlexO FOIC 4.4-RS 111.8 GTM PAM4 320 349.4061 698.8092
400G FlexO FOIC4.8-RS 55.9 GTM PAM4 160 349.4061 698.8092
400GE (Overclocking) 400GAUI-8 56.42 GTM PAM4 160 352.625 705.25
400GE (Overclocking) 400GAUI-4 112 GTM PAM4 320 350 700
Note: 112G (Overclocking) line rate configurations are not supported with Coupled MAC+PCS in the DCMAC IP Wizard. 
Note: 128GFC is only supported in faster devices.
Note: In slower devices, overclocking is only supported in Independent MAC and PCS+FEC mode. In faster devices, this restriction is removed.
Note: The transceiver interface is re-used when the DCMAC Subsystem is operating in FEC-only mode. In that mode, the DCMAC Subsystem TX path performs only the FEC encode function and the output is not necessarily directly bound for a GT transceiver. Similarly, the DCMAC Subsystem RX path performs only the FEC decode function and the input is not necessarily directly arriving from a GT transceiver.

The following table shows a list of DCMAC Subsystem-supported interface options for FEC-only mode, including the associated data rates, datapath width, and clock frequency.

Table 2. Transceiver FEC-Only Operating Modes
Operating Mode RS(528,514) RS(544,514) FEC-Only Rate (Gbps) FEC-Only Interface Data Width (Bits) FEC-Only Interface Clock (MHz) FEC-Only Logic Internal Clock (MHz)
2 x 53.125G FEC-only 53.125 2 x 160 332.03125 664.0625
2 x 56.42G FEC-only 56.42G 2 x 160 352.625 705.25
1 x 106.25G FEC-only 106.25 320 332.03125 664.0625
1 x 112G FEC-only 112G 320 350 700