User Interface - 2.3 English

Versal Adaptive SoC 600G Channelized Multirate Ethernet Subsystem (DCMAC) LogiCORE IP Product Guide (PG369)
Document ID
PG369
Release Date
2023-11-08
Version
2.3 English

Note the following:

  • 6x100GE CAUI-4, 6x100GE 100GAUI-4, and 3x200GE 200GAUI-8 configuration requires six GTYP/GTM Quads connected to the DCMAC IP. Each Quad requires a GT reference clocks (gt_ref_clk), so six GT reference clocks are required.
  • 1x400GE 400GAUI-16 configuration requires four GTYP/GTM Quads connected to the DCMAC IP. Each Quad requires a GT reference clock, so four GT reference clocks are required.
  • 6x100GE 100GAUI-2 and 3x200GE 200GAUI-4 configuration requires three GTM Quads connected to the DCMAC IP. Each Quad requires a GT reference clock (gt_ref_clk), so three GT reference clocks are required.
  • 1x400GE 400GAUI-8 configuration requires two GTM Quads connected to the DCMAC IP, so two GT reference clocks are required.
Table 1. GT Transceiver And Clock Interface I/O Ports (6x100GE Configuration)
Name Size I/O Description
gt_ref_clk0_p 1 I Differential input clk to GT
gt_ref_clk0_n 1 I Differential input clk to GT
gt_ref_clk1_p 1 I Differential input clk to GT
gt_ref_clk1_n 1 I Differential input clk to GT
gt_ref_clk2_p 1 I Differential input clk to GT
gt_ref_clk2_n 1 I Differential input clk to GT
gt_ref_clk3_p 1 I Differential input clk to GT
gt_ref_clk3_n 1 I Differential input clk to GT
gt_ref_clk4_p 1 I Differential input clk to GT
gt_ref_clk4_n 1 I Differential input clk to GT
gt_ref_clk5_p 1 I Differential input clk to GT
gt_ref_clk5_n 1 I Differential input clk to GT
gt_rxn_in0 4 I Differential serdes input to GT
gt_rxp_in0 4 I Differential serdes input to GT
gt_rxn_in1 4 I Differential serdes input to GT
gt_rxp_in1 4 I Differential serdes input to GT
gt_rxn_in2 4 I Differential serdes input to GT
gt_rxp_in2 4 I Differential serdes input to GT
gt_rxn_in3 4 I Differential serdes input to GT
gt_rxp_in3 4 I Differential serdes input to GT
gt_rxn_in4 4 I Differential serdes input to GT
gt_rxp_in4 4 I Differential serdes input to GT
gt_rxn_in5 4 I Differential serdes input to GT
gt_rxp_in5 4 I Differential serdes output to GT
gt_txn_out0 4 O Differential serdes output to GT
gt_txp_out0 4 O Differential serdes output to GT
gt_txn_out1 4 O Differential serdes output to GT
gt_txp_out1 4 O Differential serdes output to GT
gt_txn_out2 4 O Differential serdes output to GT
gt_txp_out2 4 O Differential serdes output to GT
gt_txn_out3 4 O Differential serdes output to GT
gt_txp_out3 4 O Differential serdes output to GT
gt_txn_out4 4 O Differential serdes output to GT
gt_txp_out4 4 O Differential serdes output to GT
gt_txn_out5 4 O Differential serdes output to GT
gt_txp_out5 4 O Differential serdes output to GT