The following chapter explains the AMD Versal™ adaptive SoCs Integrated 600G Interlaken with FEC example design. A packet generator and checker is used to send data packets through the segmented AXI4-Stream interface. These packets are then sent to the GT transceivers through the transceiver interface. Data is looped back external to the GT and is finally received by the packet checker through the segmented AXI4-Stream interface.
The GT sub core is always present in the example design. This example design demonstrates the functioning of the core for all supported configurations. A separate example design is generated for the FEC Only mode whose details are also covered in this section.