Interlaken Configuration Selection - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2024-01-09
Version
1.3 English

The configuration of the ILKNF subsystem is selected according to the following table.

Table 1. Interlaken Configuration Settings
ctl_core_mode[1:0] SerDes I/F Mode (Bits) 1 Supported Gearbox Mode(s) 2 Internal Bus Width (Bits) AXI Width (Bits) SerDes Rate (Gb/s) Max # Lanes
2'b00 40 67/40 512 512 12.5 12
40 67/40 512 512 25.781 8
512 6
768 8
768 10
1024 10
768 12
1024 12
80a 67/40 512 512 28.21 8
512 6
768 8
768 10
1024 10
768 12
1024 12
80 130/130 (FEC) 134/80 512 512 53.125 4
768 4
768 6
1024 6
160a 130/130 (FEC) 134/80 512 512 56.42 4
768 4
768 6
1024 6
2'b01 40 67/40 512 768 12.5 18
768 24
1024 24
2'b10 40 67/40 1024 1024 25.781 16
1536 16
1536 18
2048 18
1536 24
2048 24
80a 67/40 1024 1024 28.21 16
1536 16
1536 18
2048 18
1536 24
2048 24
2'b11 80 130/130 (FEC) 134/80 1024 1024 53.125 8
1536 8
1536 10
2048 10
1536 12
2048 12
160a 130/130 (FEC) 134/80 1024 1024 56.42 8
1536 8
1536 10
2048 10
1536 12
2048 12
  1. This column refers to the c0_ctl_tx_serdes_intf_mode[1:0] field of the CFG_C0_TX_OVERALL_REG register and the c0_ctl_rx_serdes_intf_mode[1:0] field of the CFG_C0_RX_OVERALL_REG register. These configuration controls, along with the ctl_core_mode[1:0] field of the CFG_CORE_MODE_REG register, must only be changed while no traffic is flowing through any portion of the entire hard block.
  2. This column refers to the c0_ctl_tx_gearbox_mode[1:0] field of the CFG_C0_TX_OVERALL_REG register, and the c0_ctl_rx_gearbox_mode[1:0] field of the CFG_C0_RX_OVERALL_REG register. These configuration controls, along with the ctl_core_mode[1:0] field of the CFG_CORE_MODE_REG register, must only be changed while no traffic is flowing through any portion of the entire hard block.
Note: A reset is required after a configuration change.