Interlaken Device Support - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2024-01-09
Version
1.3 English

AMD provides a range of speed grades, allowing you to trade off power and performance. Some low power parts do not support all of the Interlaken configurations.

The following table lists the configurations that are supported by all device speed grades. The GT interface is running wide, allowing the GT clock frequency to be reduced. Contrast this with Interlaken Configuration Selection, which contains the similar configurations for faster speed grades, with the GT interface running narrow.

Table 1. Configurations Supported by All Speed Grades
Max Transceiver Rate (Gb/s) Max # Lanes Aggregate BW (Gb/s) AXI Width (Bits) AXI Clock (MHz) Core Clock (MHz) GT Interface Width (Bits) GT Clock (MHz) Lane Logic Clock (MHz)
53.125 12 637.5 2048 312 623 160 332.03125 664.0625
10 531.25 2048 260 519
8 425 1536 278 416
6 318.75 1024 312 623
4 212.5 768 278 416
25.78125 24 618.75 2048 303 605 80 322.26563 644.5313
18 464.0625 2048 228 454
18 464.0625 1536 303 454
16 412.5 1536 269 403
12 309.375 1024 303 605
10 257.8125 1024 253 504
8 206.25 768 269 403
6 154.6875 512 303 403
12.5 24 300 1024 293 586 40 312.5 312.5
18 225 768 293 440
12 150 512 293 293