Reduced Fabric Clock Frequency with Low Frequency Core Clock

Reduced Fabric Clock Frequency with Low Frequency Core Clock - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID

PG371

Release Date

2024-01-09

Version

1.3 English

To support reduced fabric interface rates, you need to set the following rate adaptation fields and registers:

c0_ctl_rx_rate_adapt_inc[7:0] register field of the CFG_C0_RX_RATE_ADAPT_INC register
c0_ctl_rx_rate_adapt_dec[7:0] register field of the CFG_C0_RX_RATE_ADAPT_DEC register

The register values depend on the configuration. The following table lists values of rate adaptation registers for each configuration.

Table 1. Rate Adapter Inc/Dec Values for Low-Frequency Core Clock Interlaken Configurations
Max Transceiver Rate (Gb/s)	Max # Lanes	Aggregate BW (Gb/s)	AXI Width (Bits)	AXI Clock (MHz)	Core Clock (MHz)	GT I/F Width (Bits)	RX Rate Adapt Inc¹	RX Rate Adapt Dec²
56.42	12	677.04	2048	331	662	160	32	16
	12	677.04	1536	441	662		24	16
	10	564.2	2048	276	551		32	16
	10	564.2	1536	368	551		24	16
	8	451.36	1536	294	441		24	16
	8	451.36	1024	441	441		16	16
	6	338.52	1024	331	662		16	8
	6	338.52	768	441	662		12	8
	4	225.68	768	294	441		12	8
	4	225.68	512	441	441		8	8
53.125	12	637.5	2048	312	623	80	32	16
	12	637.5	1536	416	623		24	16
	10	531.25	2048	260	519		32	16
	10	531.25	1536	347	519		24	16
	8	425	1536	278	416		24	16
	8	425	1024	416	416		16	16
	6	318.75	1024	312	623		16	8
	6	318.75	768	416	623		12	8
	4	212.5	768	278	416		12	8
	4	212.5	512	416	416		8	8
28.21	24	677.04	2048	331	662	80	32	16
	24	677.04	1536	441	662		24	16
	18	507.78	2048	249	496		32	16
	18	507.78	1536	331	496		24	16
	16	451.36	1536	294	441		24	16
	16	451.36	1024	441	441		16	16
	12	338.52	1024	331	662		16	8
	12	338.52	768	441	662		12	8
	10	282.1	1024	277	551		16	8
	10	282.1	768	369	551		12	8
	8	225.68	768	294	441		12	8
	8	225.68	512	441	441		8	8
	6	169.26	512	331	441		8	6
25.78125	24	618.75	2048	303	605	40	32	16
	24	618.75	1536	404	605		24	16
	18	464.0625	2048	228	454		32	16
	18	464.0625	1536	303	454		24	16
	16	412.5	1536	269	403		24	16
	16	412.5	1024	403	403		16	16
	12	309.375	1024	303	605		16	8
	12	309.375	768	404	605		12	8
	10	257.8125	1024	253	504		16	8
	10	257.8125	768	337	504		12	8
	8	206.25	768	269	403		12	8
	8	206.25	512	403	403		8	8
	6	154.6875	512	303	403		8	6
12.5	24	300	1024	293	586	40	16	8
	24	300	768	391	586		12	8
	18	225	768	293	440		12	8
	12	150	512	293	293		8	8
This column refers to the `c0_ctl_rx_rate_adapt_inc[3:0]` field of the CFG_C0_RX_RATE_ADAPT_INC register. This column refers to the `c0_ctl_rx_rate_adapt_dec[3:0]` field of the CFG_C0_RX_RATE_ADAPT_DEC register.