Register Map - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)
Document ID
PG371
Release Date
2024-01-09
Version
1.3 English

The below registers are used to access the statistics counters, status signals, and control signals of GT and ILKNF. Individual bits or registers can be classified as follows:

  • STATUS: These bits are set to HIGH after a reset or read. A LOW on these bits would mean that the corresponding signal was LOW at least once since the bit was last read or reset. These registers are read-only and have to be read twice to get the current value of the signal.
  • ERROR: These bits are cleared after a reset or read. A HIGH on these bits would mean that the corresponding error was asserted at least once since the bit was the last read or reset. These registers are read-only and have to be read twice to get the current value of the signal.
  • STATISTICS: These registers are connected to accumulators. On assertion of PM tick signal, the value accumulated is loaded into the register, and the accumulator is reset. These registers are read-only.
  • CONTROL: The value written to these bits is driven on the corresponding control signal.
The below registers can be accessed through AXI4-Lite Interface:
Table 1. RESET TICK REGISTER (0x0000)
Bits Access Description
31-4 Unused Unused
3 WO Reset all internal registers and counters on c0_axi_clock domain
2 WO Reset all internal registers and counters on rx_alt_serdes_clock domain
1 WO PM Tick for counters on rx_alt_serdes_clock domain
0 WO PM Tick for counters on c0_axi_clock domain
Table 2. GT_RESET_ALL REGISTER (0x0004)
Bits Type Access Description
31-24 Unused RO Unused
23-0 CONTROL R/W Each bit represents the reset signal for the GT reset controller on the corresponding lane. Connects to gt_reset_all input of the core.
Table 3. GT_RESET_RX_DATAPATH REGISTER (0x0008)
Bits Type Access Description
31-24 Unused RO Unused
23:0 CONTROL R/W Drives gt_reset_rx_datapath_in input of the core
Table 4. GT_RESET_TX_DATAPATH REGISTER (0x000C)
Bits Type Access Description
31-24 Unused RO Unused
23:0 CONTROL R/W Drives gt_reset_tx_datapath_in input of the core
Table 5. GT_TX_RESETDONE REGISTER (0x0010)
Bits Type Access Description
31-24 Unused RO Unused
23:0 STATUS RO Connected to gt_tx_reset_done_out output of the core
Table 6. GT_RX_RESETDONE REGISTER (0x0014)
Bits Type Access Description
31-24 Unused RO Unused
23:0 STATUS RO Connected to gt_rx_reset_done_out output of the core
Table 7. GT CONTROL REGISTER
Bits Type Access Description
31:24 Unused RO  
23:17 CONTROL R/W Drives TX Post cursor pin of all connected GT channels.
16:11 CONTROL R/W Drives TX Pre cursor pin of all connected GT channels.
11:4 CONTROL R/W Drives TX Main cursor pin of all connected GT channels.
3 CONTROL R/W Drives RX CDR Hold pin of all connected GT channels.
2:0 CONTROL R/W Sets loop back mode for all connected GT channels.
Table 8. CTL_RX_FORCE_RESYNC REGISTER (0x0018)
Bits Type Access Description
31-1 Unused RO Unused
0 CONTROL R/W Drives c0_ctl_rx_force_resync input of the core
Table 9. CTL_TX_DIAGWORD_INTFSTAT REGISTER (0x001C)
Bits Type Access Description
31-1 Unused RO Unused
0 CONTROL R/W Drives c0_ctl_tx_diagword_intfstat input of the core
Table 10. CTL_TX_DIAGWORD_LANESTAT REGISTER (0x0020)
Bits Type Access Description
31-24 Unused RO Unused
23-0 CONTROL R/W Drives ctl_tx_diagword_lanestat input of the core
Table 11. CTL_TX_ENABLE REGISTER (0x0024)
Bits Type Access Description
31-1 Unused RO Unused
0 CONTROL R/W Drives c0_ctl_tx_enable input of the core
Table 12. CTL_TX_FC_STAT REGISTERS (0x0028-0x0044)
Bits Type Access Description
31-0 CONTROL R/W The 255 bit signal c0_ctl_tx_fc_stat is driven by 8 32-bit registers numbered from 0 to 7. Register 0 drives bits 31-0, Register 1 drives bit 63-32, and so on.
Table 13. CTL_TX_MUBITS REGISTER (0x0048)
Bits Type Access Description
31-8 Unused RO Unused
7-0 CONTROL R/W Drives c0_ctl_tx_mubits input of the core
Table 14. TX STATUS REGISTER (0x004C)
Bits Type Access Description
31-5 Unused RO Unused
4 ERROR RO Connected to c0_stat_tx_fifo1_oflow_err output of the core
3 ERROR RO Connected to c0_stat_tx_fifo1_uflow_err output of the core.
2 ERROR RO Connected to c0_stat_tx_fifo2_uflow_err output of the core
1 ERROR RO Connected to c0_stat_tx_overflow_err output of the core
0 ERROR RO Connected to c0_stat_tx_underflow_err output of the core
Table 15. RX STATUS REGISTER (0x0050)
Bits Type Access Description
31-5 Unused RO Unused
4 ERROR RO Connected to c0_stat_rx_burstmax_err output of the core
3 ERROR RO Connected to c0_stat_rx_overflow_err output of the core
2 ERROR RO Connected to c0_stat_rx_misaligned output of the core
1 ERROR RO Connected to c0_stat_rx_aligned_err output of the core
0 STATUS RO Connected to c0_stat_rx_aligned output of the core
Table 16. RX_SYNCED REGISTER (0x0054)
Bits Type Access Description
31-24 Unused RO Unused
23-0 STATUS RO Connected to stat_rx_synced output of the core
Table 17. RX_SYNCED ERROR REGISTER (0x0058)
Bits Type Access Description
31-24 Unused RO Unused
23-0 ERROR RO Connected to stat_rx_synced_err output of the core
Table 18. RX_WORD_SYNC REGISTER (0x005C)
Bits Type Access Description
31-24 Unused RO Unused
23-0 STATUS RO Connected to stat_rx_word_sync output of the core
Table 19. RX_DIAGWORD_LANESTAT REGISTER (0x0060)
Bits Type Access Description
31-24 Unused RO Unused
23-0 STATUS RO Status register for stat_rx_diagword_lanestat qualified with stat_rx_crc32_valid for each lane
Table 20. RX_DIAGWORD_INTFSTAT REGISTER (0x0064)
Bits Type Access Description
31-24 Unused RO Unused
23-0 STATUS RO Status register for stat_rx_diagword_intfstat qualified with stat_rx_crc32_valid for each lane
Table 21. RX_MUBITS REGISTER (0x0064)
Bits Type Access Description
31-24 Unused RO Unused
23-0 STATUS RO Status register for c0_stat_rx_mubits qualified with c0_stat_rx_mubits_updated
Table 22. RX_DESCRAM_ERR REGISTER (0x0064)
Bits Type Access Description
31-24 Unused RO Unused
23-0 ERROR RO Connected to stat_rx_descram_err output of the core
Table 23. RX_BAD_TYPE_ERR LANE N REGISTER (0x0070-0x00CC)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times Bad type error (stat_rx_bad_type_err ) has occurred for lane N. The number of registers present depends on the number of lanes.
Table 24. RX_CRC32_ERR LANE N REGISTER (0x00D0-0x012C)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times CRC32 error (stat_rx_crc32_err ) has occurred for lane N. The number of registers present depends on the number of lanes .
Table 25. RX_FRAMING_ERR LANE N REGISTER (0x0130-0x018C)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times Framing error (stat_rx_framing_err ) has occurred for lane N. The number of registers present depends on the number of lanes.
Table 26. RX_BURST_ERR REGISTER (0x0190)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times RX Burst error (stat_rx_burst_err ) has occurred
Table 27. RX ERROR REGISTER (0x0194)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times RX error (stat_rx_err ) has occurred
Table 28. RX MEOP ERROR REGISTER (0x0198)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times RX Missing EOP error (c0_stat_rx_meop_err ) has occurred
Table 29. RX MSOP ERROR REGISTER (0x019C)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times RX Missing SOP error (c0_stat_rx_msop_err ) has occurred
Table 30. TX BURST ERROR REGISTER (0x01A0)
Bits Type Access Description
31-0 STATISTICS RO Counts the number of times TX Burst error (c0_stat_tx_burst_err) has occurred
Table 31. STAT_RX_FC_STAT REGISTERS (0x01A4-0x01C0)
Bits Type Access Description
31-0 N/A RO Eight such registers combined connect to c0_stat_rx_fc_stat[255:0] output of the core. The lowest address contains the value of c0_stat_rx_fc_stat[31:0]. Similarly, the highest address contains the value of c0_stat_rx_fc_stat[255:224]
Table 32. RX FEC STATUS REGISTER 0-5 (0x01C4,0x020C,0x0254,0x029C,0x02E4,0x032C)
Bits Type Access Description
31-5 Unused RO Not used
4-1 STATUS RO Indicates whether the alignment markers for the FEC instance have been locked
0 STATUS RO Indicates whether the FEC instance has aligned.