Synthesizing and Implementing the Example Design - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2024-01-09
Version
1.3 English
To run synthesis and implementation on the example design in AMD Vivado™ Design Suite, perform the following steps:
  1. Go to the XCI file, right-click and select Open IP Example Design. A new Vivado tool window opens with the project name example_project in the project directory.
  2. In the Flow Navigator, click Run Synthesis > Run Implementation.
  3. A C File named ilknf_exdes_test.c is generated in the following folder: <project_name>/<project_name>.gen/sources_1/bd/<ip_name>_exdes_support/ip/<ip_name>_exdes_support_<ip_name>_core_0/sample_c_files. This file contains basic functions such as packet scheduling, alignment detection and statistics comparison and reporting. This file is also generated for the FEC-Only example design.
Tip: Click Run Implementation first to run both synthesis and implementation. Click Generate Bitstream to run synthesis, implementation, and then bitstream.
Tip: For step-by-step guide to perform example design synthesis, implementation, and validation of the ILKNF Example Design on VPK180 board, se Versal Devices Integrated 100G Multirate Ethernet MAC (MRMAC) LogiCORE IP Product Guide (PG314).

While the steps to validate ILKNF on VPK180 are similar to that of MRMAC/DCMAC, the user must make necessary changes to example design to ensure that the reference clock for each GT in the design is sourced from a GT_REFCLK site whose pins are connected to an oscillator on board.