Transceiver (SerDes) Interface - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2024-01-09
Version
1.3 English

The clock and data connections between the ILKNF transceiver interface and the GT transceivers varies depending on the selected GT technology and the configured operating mode. This section describes the connectivity between the ILKNF and the GT transceivers.

Note: In this table, <N> is the SerDes data bus number 0 to 23.
Table 1. Transceiver Interface Signal Descriptions
Port Name Clock Domain I/O Description
tx_serdes_data<N>[79:0] tx_serdes_clk[0] / tx_alt_serdes_clk[0] O In Interlaken mode, this is the data bus to the serial transceiver.
tx_fec0_slice0_dout_start tx_serdes_clk[0] / tx_alt_serdes_clk[0] O When configured for ILKN+FEC mode, indicates start of codeword on tx_serdes_data0.
tx_fec1_slice0_dout_start tx_serdes_clk[0] / tx_alt_serdes_clk[0] O When configured for ILKN+FEC mode, indicates start of codeword on tx_serdes_data2 (c0_ctl_tx_serdes_intf_mode[0] = 1) or tx_serdes_data4 (c0_ctl_tx_serdes_intf_mode[1] = 1).
tx_fec2_slice0_dout_start tx_serdes_clk[0] / tx_alt_serdes_clk[0] O When configured for ILKN+FEC mode, indicates start of codeword on tx_serdes_data4 (c0_ctl_tx_serdes_intf_mode[0] = 1) or tx_serdes_data8 (c0_ctl_tx_serdes_intf_mode[1] = 1).
tx_fec3_slice0_dout_start tx_serdes_clk[0] / tx_alt_serdes_clk[0] O When configured for ILKN+FEC mode, indicates start of codeword on tx_serdes_data6 (c0_ctl_tx_serdes_intf_mode[0] = 1) or tx_serdes_data12 (c0_ctl_tx_serdes_intf_mode[1] = 1).
tx_fec4_slice0_dout_start tx_serdes_clk[0] / tx_alt_serdes_clk[0] O When configured for ILKN+FEC mode, indicates start of codeword on tx_serdes_data8 (c0_ctl_tx_serdes_intf_mode[0] = 1) or tx_serdes_data16 (c0_ctl_tx_serdes_intf_mode[1] = 1).
tx_fec5_slice0_dout_start tx_serdes_clk[0] / tx_alt_serdes_clk[0] O When configured for ILKN+FEC mode, indicates start of codeword on tx_serdes_data10 (c0_ctl_tx_serdes_intf_mode[0] = 1) or tx_serdes_data20 (c0_ctl_tx_serdes_intf_mode[1] = 1).
rx_serdes_data<N>[79:0] rx_serdes_clk[0] / rx_alt_serdes_clk[0] I In Interlaken mode, this is the data bus from the serial transceiver.