User Parameters - 1.3 English

Versal Adaptive SoC Integrated 600G Interlaken with FEC Subsystem Product Guide (PG371)

Document ID
PG371
Release Date
2024-01-09
Version
1.3 English

The following table shows the relationship between the fields in the AMD Vivado™ IDE and the user parameters (which can be viewed in the Tcl Console).

Table 1. User Parameters
Parameter Description Default Value Options/Range
System Configuration
ILKNF Preset Interlaken Configuration Preset 1x600G_Interlaken_FEC_12x53.13G_GTM_160b
Data Path Function Data Path Function Interlaken without FEC
Interlaken Core Mode Interlaken Core mode 1x600G 1x600G, 1x300G
AXI-S User Interface Width Segmented AXI4-Stream User Interface Width 2048 2048, 1536, 1024, 768,512
ILKN Core Selection Location of ILKNF Hard Block ILKNF_X0Y0 Device Dependent
Physical Layer Configuration
Number of Lanes Number of Interlaken/SerDes Lanes used by the core 24 24, 12, 8, 6, 4, 2
SerDes Lane Line Rate Max Supported Line-rate of each Interlaken/SerDes Lane 28.21 25.78125, 28.21, 53.125, 56.42
Enable Low latency mode Set the rate adapter values for given configuration to operate in low latency mode as per table 7. -- --
Link Layer Configuration
RX Dataflow Mode Interlaken Packet mode Burst Interleaved Mode Burst Interleaved Mode, Packet Mode
Burst Max Maximum size of a data burst 256 256, 512, 1024, 2048
Burst Short Minimum size of a data burst 64 64
Meta Frame Meta Frame length 2048 256–8192
Channels Maximum number of TX and RX data channels for Interlaken Core 256 256, 512, 1024, 2048
FEC Configuration
FEC Configuration Table Sets the Operating Mode of each FEC Encoder (TX) and Decoder (RX)
GT Info and Params
GT Type Type of GT used GTM GTM, GTYP
GT RefClk GT Reference clock frequency 322.265625 156.25, 312.5, 322.265635, 161.1328125
GT Line Encoding GT Line encoding NRZ PAM4, NRZ
GT Mode Narrow/Wide GT User Interface Wide Mode Narrow Mode, Wide Mode
Number of GT Pipeline registers Number of pipeline registers on GT data path. 2 or 0 0-16