The AXI4-Lite interface has its own clock and reset. The AXI4-Lite clock (s_axi_aclk) is independent of the
remainder of the HSC Subsystem clocks and can be any frequency up to a maximum of 300
MHz.
Important: The AXI4-Lite clock must be present and stable
for the HSC Subsystem to operate. An interruption in the AXI4-Lite clock
is likely to result in an unrecoverable internal HSC Subsystem error. When the AXI4-Lite clock has returned and is stable, this requires a full
reset-sequence to bring the HSC Subsystem back to a stable condition.
Asserting the AXI4-Lite
s_axi_areset pin results in:
- A reset of the AXI4-Lite port and HSC Subsystem APB3 control logic, stopping any in-flight writes/ reads.
- A reset of the soft reset registers found in GLOBAL_CONTROL_REG_TX GLOBAL_CONTROL_REG_RX.
An AXI4-Lite reset does not reset the internal configuration registers.