The HSC Subsystem contains a soft logic 32-bit AXI4-Lite interface block to allow access to the integrated IP's APB3 interface. Through the AXI4-Lite interface, you can access the internal configuration, status, and statistics registers. For more details on the AXI4-Lite interface, see the AXI to APB Bridge LogiCORE IP Product Guide (PG073).
| Port Name | I/O | Description |
|---|---|---|
| s_axi_aclk | I | This clock is used for both the AXI4-Lite
bridge Soft Logic and HSC Subsystem APB3 port clock. Note: The
s_axi_clk must be present for the HSC Subsystem to function. If this
clock is interrupted, the HSC Subsystem enters an error state.
|
| s_axi_areset | I | Active-High reset for the AXI4-Lite port. Asserting this reset alters the Port control logic and stops any in-flight writes/reads. It does not reset the internal configuration registers with exceptions listed below. |
| s_axi_* | I/O | See the AXI to APB Bridge LogiCORE IP Product Guide (PG073) and Vivado Design Suite: AXI Reference Guide (UG1037). |
| s_axi_pslverr | O |
HSC Subsystem
AXI4-Lite slave error indication. This signal is Low during
successful operation. When High, the signal indicates an AXI bus
protocol error has occurred. Note: Writes or reads to
non-existent/invalid register locations, nor a port being held
in reset does not trigger a slave error
indication.
|
A complete description of the register map and the individual registers can be found in the Register Space section.