Accessing Statistics Counters - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)
Document ID
PG372
Release Date
2024-01-30
Version
1.0 English
The HSC Subsystem maintains statistics counters for all SecYs and internals SCs (i.e. SCs associated with internals SAs) in its internal tables. You can read or read-and-clear these statistics through indirect register access.

Following is the procedure to read TX SC statistics for an internal SC with index SC_INDEX[8:0].

  1. Set the TX_INDIRECT_AXS_CTL_REG register:
    1. Set the tx_ind_axs_ctrl_wrn field to 0 (TX_INDIRECT_AXS_CTL_REG[1]=0) to indicate a read function.
    2. Set tx_ind_axs_ctrl_grp = 2'b11 (TX_INDIRECT_AXS_CTL_REG[3:2] = 2’b11) to indicate indirect access to the TX SC statistics table.
    3. Set tx_ind_axs_ctrl_keep = 1'b0/1'b1 (TX_INDIRECT_AXS_CTL_REG[4] = 1’b0/1’b1) to clear/keep the corresponding SC statistics after read.
    4. Set tx_ind_axs_ctrl_num = {1'b0, SC_INDEX[8:0]} (TX_INDIRECT_AXS_CTL_REG[17:8] = {1’b0, SC_INDEX[8:0]}) if two SAs per SC is supported. Otherwise, set tx_ind_axs_ctrl_num = {2'b00, SC_INDEX[7:0]} (RX_INDIRECT_AXS_CTL_REG[17:8] = {2’b00, SC_INDEX[7:0]})
    5. Set the tx_ind_axs_ctrl_ena field to 1 (TX_INDIRECT_AXS_CTL_REG[0]=1).
  2. Wait until the tx_ind_axs_ctrl_ena bit is cleared (or a pulse is generated on the stat_rsvd_out_tx_top[120] pin).
  3. Read the corresponding SC statistics from the following registers:
    1. TX_INDIRECT_AXS_RDATA_REG_LSB = STAT_TX_SC_PROTECTED_PACKETS[31:0]
    2. TX_INDIRECT_AXS_RDATA_REG_MID1 = STAT_TX_SC_PROTECTED_PACKETS[63:32]
    3. TX_INDIRECT_AXS_RDATA_REG_MID2 = STAT_TX_SC_ENCRYPTED_PACKETS[31:0]
    4. TX_INDIRECT_AXS_RDATA_REG_MID3 = STAT_TX_SC_ENCRYPTED_PACKETS[63:32]

Following is the procedure to read TX SecY/channel statistics for SECY_INDEX[5:0].

  1. Set the TX_INDIRECT_AXS_CTL_REG register:
    1. Set the tx_ind_axs_ctrl_wrn field to 0 (TX_INDIRECT_AXS_CTL_REG[1]=0) to indicate a read function.
    2. Set tx_ind_axs_ctrl_grp = 2'b10 (TX_INDIRECT_AXS_CTL_REG[3:2] = 2’b10) to indicate indirect access to the SecY statistics table.
    3. Set tx_ind_axs_ctrl_keep = 1'b0/1'b1 (TX_INDIRECT_AXS_CTL_REG[4] = 1’b0/1’b1) to clear/keep the corresponding SC statistics after read.
    4. Set tx_ind_axs_ctrl_num = {4'h0, SECY_INDEX[5:0]} (TX_INDIRECT_AXS_CTL_REG[17:8] = {4’h0, SECY_INDEX[5:0]}).
    5. Set the tx_ind_axs_ctrl_ena field to 1 (TX_INDIRECT_AXS_CTL_REG[0]=1).
  2. Wait until the tx_ind_axs_ctrl_ena bit is cleared (or a pulse is generated on the stat_rsvd_out_tx_top[120] pin).
  3. Read the corresponding SC statistics from the following registers:
    1. TX_INDIRECT_AXS_RDATA_REG_LSB = STAT_TX_SECY_UNTAGGED_PACKETS[31:0]
    2. TX_INDIRECT_AXS_RDATA_REG_MID1 = STAT_TX_SECY_UNTAGGED_PACKETS[63:32]
    3. TX_INDIRECT_AXS_RDATA_REG_MID2 = STAT_TX_SECY_TOO_LONG_PACKETS[31:0]
    4. TX_INDIRECT_AXS_RDATA_REG_MID3 = STAT_TX_SECY_TOO_LONG_PACKETS[63:32]
    5. TX_INDIRECT_AXS_RDATA_REG_MID4 = STAT_TX_SECY_PROTECTED_OCTETS[31:0]
    6. TX_INDIRECT_AXS_RDATA_REG_MID5 = STAT_TX_SECY_PROTECTED_OCTETS[63:32]
    7. TX_INDIRECT_AXS_RDATA_REG_MID6 = STAT_TX_SECY_ENCRYPTED_OCTETS[31:0]
    8. TX_INDIRECT_AXS_RDATA_REG_MSB7 = STAT_TX_SECY_ENCRYPTED_OCTETS[63:32]

Following is the procedure to read RX SC statistics with index SC_INDEX[8:0].

  1. Set the RX_INDIRECT_AXS_CTL_REG register:
    1. Set the rx_ind_axs_ctrl_wrn field to 0 (RX_INDIRECT_AXS_CTL_REG[1]=0) to indicate a read function.
    2. Set rx_ind_axs_ctrl_grp = 2'b11 (RX_INDIRECT_AXS_CTL_REG[3:2] = 2’b11) to indicate indirect access to the RX SC statistics table.
    3. Set rx_ind_axs_ctrl_keep = 1'b0/1'b1 (RX_INDIRECT_AXS_CTL_REG[4] = 1’b0/1’b1) to clear/keep the corresponding SC statistics after read.
    4. Set rx_ind_axs_ctrl_num = {1'b0, SC_INDEX[8:0]} (RX_INDIRECT_AXS_CTL_REG[17:8] = {1’b0, SC_INDEX[8:0]}) if two SAs per SC is supported. Otherwise, set rx_ind_axs_ctrl_num = {2'b00, SC_INDEX[7:0]} (RX_INDIRECT_AXS_CTL_REG[17:8] = {2’b00, SC_INDEX[7:0]}).
    5. Set the rx_ind_axs_ctrl_ena field to 1 (RX_INDIRECT_AXS_CTL_REG[0]=1).
  2. Wait until the rx_ind_axs_ctrl_ena bit is cleared (or a pulse is generated on the stat_rsvd_out_rx_top[120] pin).
  3. Read the corresponding SC statistics from the following registers:
    1. RX_INDIRECT_AXS_RDATA_REG_LSB = STAT_RX_SC_DELAYED_PACKETS[31:0]
    2. RX_INDIRECT_AXS_RDATA_REG_MID1 = STAT_RX_SC_DELAYED_PACKETS[63:32]
    3. RX_INDIRECT_AXS_RDATA_REG_MID2 = STAT_RX_SC_LATE_PACKETS[31:0]
    4. RX_INDIRECT_AXS_RDATA_REG_MID3 = STAT_RX_SC_LATE_PACKETS[63:32]
    5. RX_INDIRECT_AXS_RDATA_REG_MID4 = STAT_RX_SC_NOT_VALID_PACKETS[31:0]
    6. RX_INDIRECT_AXS_RDATA_REG_MID5 = STAT_RX_SC_NOT_VALID_PACKETS[63:32]
    7. RX_INDIRECT_AXS_RDATA_REG_MID6 = STAT_RX_SC_INVALID_PACKETS[31:0]
    8. RX_INDIRECT_AXS_RDATA_REG_MID7 = STAT_RX_SC_INVALID_PACKETS[63:32]
    9. RX_INDIRECT_AXS_RDATA_REG_MID8 = STAT_RX_SC_UNCHECKED_PACKETS[31:0]
    10. RX_INDIRECT_AXS_RDATA_REG_MID9 = STAT_RX_SC_UNCHECKED_PACKETS[63:32]
    11. RX_INDIRECT_AXS_RDATA_REG_MID10 = STAT_RX_SC_OK_PACKETS[31:0]
    12. RX_INDIRECT_AXS_RDATA_REG_MID11 = STAT_RX_SC_OK_PACKETS[63:32]

The following is the procedure to read RX SecY statistics with index SECY_INDEX[5:0].

  1. Set the RX_INDIRECT_AXS_CTL_REG register:
    1. Set the rx_ind_axs_ctrl_wrn field to 0 (RX_INDIRECT_AXS_CTL_REG[1]=0) to indicate a read function.
    2. Set rx_ind_axs_ctrl_grp = 2'b10 (RX_INDIRECT_AXS_CTL_REG[3:2] = 2’b10) to indicate the indirect access to the RX SecY statistics table.
    3. Set rx_ind_axs_ctrl_keep = 1'b0/1'b1 (RX_INDIRECT_AXS_CTL_REG[4] = 1’b0/1’b1) to clear/keep the corresponding SecY statistics after read.
    4. Set rx_ind_axs_ctrl_num = {4'h0, SECY_INDEX[5:0]} (RX_INDIRECT_AXS_CTL_REG[17:8] = {4’h0, SECY_INDEX[5:0]}).
    5. Set the rx_ind_axs_ctrl_ena field to 1 (RX_INDIRECT_AXS_CTL_REG[0]=1).
  2. Wait until the rx_ind_axs_ctrl_ena bit is cleared (or a pulse is generated on the stat_rsvd_out_rx_top[120] pin).
  3. Read the corresponding SecY statistics from the following registers:
    1. RX_INDIRECT_AXS_RDATA_REG_LSB = STAT_RX_SECY_UNTAGGED_PACKETS[31:0]
    2. RX_INDIRECT_AXS_RDATA_REG_MID1 = STAT_RX_SECY_UNTAGGED_PACKETS[63:32]
    3. RX_INDIRECT_AXS_RDATA_REG_MID2 = STAT_RX_SECY_NO_TAG_PACKETS[31:0]
    4. RX_INDIRECT_AXS_RDATA_REG_MID3 = STAT_RX_SECY_NO_TAG_PACKETS[63:32]
    5. RX_INDIRECT_AXS_RDATA_REG_MID4 = STAT_RX_SECY_BAD_TAG_PACKETS[31:0]
    6. RX_INDIRECT_AXS_RDATA_REG_MID5 = STAT_RX_SECY_BAD_TAG_PACKETS[63:32]
    7. RX_INDIRECT_AXS_RDATA_REG_MID6 = STAT_RX_SECY_NO_SA_PACKETS[31:0]
    8. RX_INDIRECT_AXS_RDATA_REG_MID7 = STAT_RX_SECY_NO_SA_PACKETS[63:32]
    9. RX_INDIRECT_AXS_RDATA_REG_MID8 = STAT_RX_SECY_NO_SA_ERROR_PACKETS[31:0]
    10. RX_INDIRECT_AXS_RDATA_REG_MID9 = STAT_RX_SECY_NO_SA_ERROR_PACKETS[63:32]
    11. RX_INDIRECT_AXS_RDATA_REG_MID10 = STAT_RX_SECY_VALIDATED_OCTETS[31:0]
    12. RX_INDIRECT_AXS_RDATA_REG_MID11 = STAT_RX_SECY_VALIDATED_OCTETS[63:32]
    13. RX_INDIRECT_AXS_RDATA_REG_MID12 = STAT_RX_SECY_DECRYPTED_OCTETS[31:0]
    14. RX_INDIRECT_AXS_RDATA_REG_MSB13 = STAT_RX_SECY_DECRYPTED_OCTETS[63:32]