Applications - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

The HSC Subsystem is a highly flexible cryptography (crypto) engine supporting encryption and decryption applications that require a very high bit rate such as:

  • Communications equipment (switches, routers, network appliances) operating as part of a Data Center Interconnect (DCI)
  • Ethernet Data Encryption (EDE) frame forwarding devices
  • SmartNIC (Network Interface Card) running crypto services on inline traffic flows between the network (eg., Ethernet) and host (for example, PCIe® )
  • Optical Transport Network (OTN) transmission
  • Crypto offload where the crypto application is entirely contained within the server and ingress/egress HSC Subsystem traffic runs solely over the host interface (for example, PCIe)
  • Tandem intrusion detection monitoring in devices built using stacked silicon interconnect (SSI) technology, where packet statistics of two identical flows, each with ingress/egress traffic within their own die, are monitored as a means of intrusion detection

The HSC Subsystem can be applied in solutions that demand AES-128 or AES-256 encryption using either MACsec, IPsec, BulkCrypto, or BulkECB methods.