CAVP Test Execution Procedures - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

The basic steps to enter CAVP mode for a port, execute a CAVP test on that port, and exit CAVP mode for a port are provided in the procedures below. Note that the order of programming is important in several cases (as noted by the numbered order). The example uses the Encryption register names but applies equally to the Decryption path when the CAVP_RX_DEC_* registers are used. Further details on the fields can be found in the detailed register description.