Channelized 400G Signaling - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

Channelized Mode 400G operation uses a 1024-bit data bus. Up to 40 channels are supported with a total capacity 400 Gb/s.

Table 1. Channelized 400G Signaling
Port Segment(s) Interface Function Signaling
0 M=0…7 Encryption Ingress (ENC_IGR) valid enc_igr_axis_tvalid_0
channel_id enc_igr_axis_tid
skip_req enc_igr_axis_skip_req
skip_id enc_igr_axis_skip_id[5:0]
seg<M>_data[127:0] enc_igr_axis_tdata_<M>[127:0]
seg<M>_ena enc_igr_axis_tuser_ena<M>
seg<M>_sop enc_igr_axis_tuser_sop<M>
seg<M>_eop enc_igr_axis_tuser_eop<M>
seg<M>_err enc_igr_axis_tuser_err<M>
seg<M>_mty enc_igr_axis_tuser_mty<M>
Encryption Egress (ENC_EGR) valid enc_egr_axis_tvalid_0
seg<M>_data[127:0] enc_egr_axis_tdata_<M>[127:0]
seg<M>_ena enc_egr_axis_tuser_ena<M>
seg<M>_sop enc_egr_axis_tuser_sop<M>
seg<M>_eop enc_egr_axis_tuser_eop<M>
seg<M>_err enc_egr_axis_tuser_err<M>
seg<M>_mty enc_egr_axis_tuser_mty<M>
Decryption Ingress (DEC_IGR) valid dec_igr_axis_tvalid_0
channel_id dec_igr_axis_tid
skip_req dec_igr_axis_skip_req
skip_id dec_igr_axis_skip_id[5:0]
seg<M>_data[127:0] dec_igr_axis_tdata_<M>[127:0]
seg<M>_ena dec_igr_axis_tuser_ena<M>
seg<M>_sop dec_igr_axis_tuser_sop<M>
seg<M>_eop dec_igr_axis_tuser_eop<M>
seg<M>_err dec_igr_axis_tuser_err<M>
seg<M>_mty dec_igr_axis_tuser_mty<M>
Decryption Egress (DEC_EGR) valid dec_egr_axis_tvalid_0
seg<M>_data[127:0] dec_egr_axis_tdata_<M>[127:0]
seg<M>_ena dec_egr_axis_tuser_ena<M>
seg<M>_sop dec_egr_axis_tuser_sop<M>
seg<M>_eop dec_egr_axis_tuser_eop<M>
seg<M>_err dec_egr_axis_tuser_err<M>
seg<M>_mty dec_egr_axis_tuser_mty<M>
  1. <M> is the segment number 0 to 7.