Channelized Mode - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

In Channelized mode, the data on the encryption egress AXI4-Stream interface in a given active cycle is associated with the channel ID specified by the enc_egr_axis_tid[5:0] output port. The data is transferred from the HSC Subsystem to the user logic whenever enc_igr_axis_tvalid_0 is asserted.

If you do not respond to skip requests on the encryption ingress interface, the internal per-channel buffer may overflow. If an overflow occurs for a given channel, the HSC Subsystem asserts stat_rsvd_out_tx_top[65] during an active cycle on encryption egress to indicate the overflow. Note that, similar to other egress signals, stat_rsvd_out_tx_top[65] is aligned with enc_egr_axis_tid[5:0]. In case of overflow, the corresponding channel must be reset/flushed before being used again.

Similar to the 400G Fixed Port mode, in 400G Channelized mode, the upper or lower four segments of the egress AXI4-Stream bus may be idle during an active cycle. The other four segments which contain valid data may also start with idle segments followed by SOP.

In 400G Channelized mode, the HSC Subsystem may send out a maximum of two SOPs and three EOPs in any given active cycle.

In 400G Channelized Mode (or 1x400G Fixed Mode), there may be four idle segments in the middle of a packet on either the lower half (segments 0 to 3) or upper half (segments 4 to 7) of the encryption egress AXI4-Stream data bus.

Note: Due to buffering, protocol overhead insertion, and clock domain crossing logic, data words might be packed into different segments between encryption ingress and egress AXI4-Stream interfaces in Fixed Port and Channelized modes. For example, if SOP for a packet appears on segment 0 on encryption ingress AXI4-Stream interface, the SOP for the same packet may appear on segment 1 on encryption egress AXI4-Stream interface.