Clocks - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID

PG372

Release Date

2024-01-30

Version

1.0 English

The following table lists the clocks that are present in the HSC Subsystem.

Table 1. Clocks
Clock	Port	Description
AXI4-Lite	s_axi_clk	AXI4-Lite processor interface clock.
AXI	enc_igr_axis_clk	Encryption Path Ingress AXI4-Stream clock.
AXI	enc_egr_axis_clk	Encryption Path Egress AXI4-Stream clock.
AXI	dec_igr_axis_clk	Decryption Path Ingress AXI4-Stream clock.
AXI	dec_egr_axis_clk	Decryption Path Egress AXI4-Stream clock.
core	enc_core_clk	Encryption Path high-speed clock which drives the HSC Subsystem internals.
core	dec_core_clk	Decryption Path high-speed clock which drives the HSC Subsystem internals.