Configuring Cipher Keys for Internal SAs - 1.0 English

The cipher key for an internal SA is configured through indirect register access. Follow these steps to configure K[255:0] for internal SA with index of SA_INDEX[9:0] for encryption:

1. Set the 256-bit cipher key as follows:
   1. TX_INDIRECT_AXS_WDATA_REG_LSB[31:0] = {K[231:224], K[239:231], K[247:240], K[255:248]}
   2. TX_INDIRECT_AXS_WDATA_REG_MID1[31:0] = {K[199:192], K[207:200], K[215:208], K[223:216]}
   3. TX_INDIRECT_AXS_WDATA_REG_MID2[31:0] = {K[167:160], K[175:168], K[183:176], K[191:184]}
   4. TX_INDIRECT_AXS_WDATA_REG_MID3[31:0] = {K[135:128], K[143:136], K[:151:144], K[159:152]}
   5. TX_INDIRECT_AXS_WDATA_REG_MID4[31:0] = {K[103:96], K[111:104], K[119:112], K[127:120]}
   6. TX_INDIRECT_AXS_WDATA_REG_MID5[31:0] = {K[71:64], K[79:72], K[87:80], K[95:88]}
   7. TX_INDIRECT_AXS_WDATA_REG_MID6[31:0] = {K[39:32], K[47:40], K[55:48], K[63:56]}
   8. TX_INDIRECT_AXS_WDATA_REG_MSB7[31:0] = {K[7:0], K[15:8], K[23:16], K[31:24]}
2. Set the TX_INDIRECT_AXS_CTL_REG register:
   1. Set the tx_ind_axs_ctrl_wrn field to 1 (TX_INDIRECT_AXS_CTL_REG[1]=1) to indicate a write function.
   2. Set tx_ind_axs_ctrl_grp = 2’b00 (TX_INDIRECT_AXS_CTL_REG[3:2] = 2’b00) to indicate the indirect access to the encryption SA keys table.
   3. Set tx_ind_axs_ctrl_num = SA_INDEX[9:0] (TX_INDIRECT_AXS_CTL_REG[17:8] = SA_INDEX[9:0]).
   4. Set the tx_ind_axs_ctrl_ena field to 1 (TX_INDIRECT_AXS_CTL_REG[0]=1)
3. When the tx_ind_axs_ctrl_ena bit is cleared (or a pulse is generated on the stat_rsvd_out_tx_top[120] pin), it indicates that the cipher key is successfully configured for the internal SA with the index SA_INDEX[9:0].

The following steps describe how to configure a 128-bit key (K[127:0) for the Internal SA with the index SA_INDEX[9:0].

1. Set the 128-bit cipher key as follows:
   1. TX_INDIRECT_AXS_WDATA_REG_LSB[31:0] = {K[103:96], K[111:104], K[119:112], K[127:120]}
   2. TX_INDIRECT_AXS_WDATA_REG_MID1[31:0] = {K[71:64], K[79:72], K[87:80], K[95:88]}
   3. TX_INDIRECT_AXS_WDATA_REG_MID2[31:0] = {K[39:32], K[47:40], K[55:48], K[63:56]}
   4. TX_INDIRECT_AXS_WDATA_REG_MID3[31:0] = {K[7:0], K[15:8], K[23:16], K[31:24]}
   5. • TX_INDIRECT_AXS_WDATA_REG_MID4[31:0] = 32’d0
      • TX_INDIRECT_AXS_WDATA_REG_MID5[31:0] = 32’d0
      • TX_INDIRECT_AXS_WDATA_REG_MID6[31:0] = 32’d0
      • TX_INDIRECT_AXS_WDATA_REG_MSB7[31:0] = 32’d0

      It is recommended to initialize the unused bits of the key as these are used to calculate the CRC32 digest value of the key. You should know the value of the unused bits of the key to validate the key write function through the CRC32 digest value. See Validating Internal Key Writes.

2. Similar to Step 2 for 256-bit keys.
3. Similar to Step 3 for 256-bit keys.