Decryption Egress Segmented AXI4-Stream Interface Signal Descriptions - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)
Document ID
PG372
Release Date
2024-01-30
Version
1.0 English
Table 1. Decryption Egress Segmented AXI4-Stream Interface Signal Descriptions
Port Name Clock Domain I/O Description
dec_egr_axis_tdata<M>[127:0] dec_egr_axis_clk O Decryption Egress AXI Segment <M> data:

Byte 0 of data on this segment is mapped to bits [7:0] and byte 15 is mapped to bits [127:120].
dec_egr_axis_tid[5:0] dec_egr_axis_clk O Decryption Egress Channel ID:

This signal represents the channel ID of the data presented on decryption egress AXI4-Stream bus. This signal is valid only in the channelized mode.
dec_egr_axis_tuser_ena<M> dec_egr_axis_clk O Per-segment enable
dec_egr_axis_tuser_eop<M> dec_egr_axis_clk O Segment End-of-Packet indicator:

Only valid for enabled segments.
dec_egr_axis_tuser_err<M> dec_egr_axis_clk O Egress Segment Error indicator:

This signal indicated that the packet ending on segment <M> has error. The error signal could be pass through error. In IPsec, the error signal is asserted if the length of the ESP packet is not a multiple of 4 bytes or the number of padding bytes is greater than 16. This signal is valid only during the end of packet.
dec_egr_axis_tuser_mty<M>[3:0] dec_egr_axis_clk O Segment Empty Bytes indicator:

Only valid for enabled EOP segments.
dec_egr_axis_tuser_sop<M> dec_egr_axis_clk O Segment Start-of-Packet indicator:

Only valid for enabled segments.
dec_egr_axis_tvalid_<N> dec_egr_axis_clk O Standard AXI Valid:

This signal validates entire decryption egress AXI4-Stream bus for Port <N>.
stat_rsvd_out_rx_top[119:0] dec_egr_axis_clk O Bit [65]: This signal is the buffer overflow signal in Channelized mode. If you do not respond to skip requests from the core in Channelized mode, the internal per-channel buffer may overflow. In that case, this signal is asserted during an active cycle on the decryption egress side aligned with dec_egr_axis_tid[5:0]. When an overflow occurs in Channelized mode, the corresponding channel must be reset/flushed before being used again.

Other bits are reserved. This signal must be ignored in Fixed Port mode.
  1. <N> = port number 0-3 and <M> is the segment number 0 to 7.