| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| dec_igr_axis_skip_id[5:0] | dec_igr_axis_clk | O | Decryption Skip ID: This signal represents the channel ID for which a skip cycle has been requested. |
| dec_igr_axis_skip_req | dec_igr_axis_clk | O | Decryption AXI4-Stream Skip
Request: When asserted, this signal indicates that the decryption core has at least a full cycle worth of data accumulated internally for the channel specified by dec_igr_axis_skip_id[5:0]. Therefore you must skip sending data for that channel during a future calendar slot to prevent overflow. The skip requests are treated as pulse signals so a cycle of skip response is expected for each cycle of assertion. This signal is only valid in channelized mode. |
| dec_igr_axis_taf_<N> | dec_igr_axis_clk | O | Almost full indicator: Provided as an advance warning that _tready is deasserted if there is no break in incoming client data. |
| dec_igr_axis_tdata<M>[127:0] | dec_igr_axis_clk | I | Decryption Ingress AXI Segment <M> Data: Byte 0 of data on this segment is mapped to bits [7:0] and byte 15 is mapped to bits [127:120]. |
| dec_igr_axis_tid[5:0] | dec_igr_axis_clk | I | Channel ID for client transaction: Only used in Channelized Mode. |
| dec_igr_axis_tready_<N> | dec_igr_axis_clk | O | AXI TREADY: Asserted to indicate acceptance of data. |
| dec_igr_axis_tuser_ena<M> | dec_igr_axis_clk | I | Segment enable: Deasserted to indicate per-segment IDLE. |
| dec_igr_axis_tuser_eop<M> | dec_igr_axis_clk | I | Segment End-of-Packet indicator: Only valid for enabled segments. |
| dec_igr_axis_tuser_err<M> | dec_igr_axis_clk | I | Segment Error indicator. |
| dec_igr_axis_tuser_mty<M>[3:0] | dec_igr_axis_clk | I | Segment Empty Bytes indicator: Only valid for enabled EOP segments. |
| dec_igr_axis_tuser_sop<M> | dec_igr_axis_clk | I | Segment Start-of-Packet indicator: Only valid for enabled segments. |
| dec_igr_axis_tvalid_<N> | dec_igr_axis_clk | I | Valid signal for the AXI bus. |
| dec_igr_ch_flush[3:0] | dec_igr_axis_clk | I | Per-channel flush. Active-High: If the HSC Subsystem is configured to channelized mode, reset is applied to the channel identified by dec_igr_axis_tid when bit 0 is asserted. In fixed port mode, assert the pin corresponding to the desired port to cause reset. |
| stat_rsvd_out_rx_top[127:120] | dec_igr_axis_clk | O |
Bit [120]: This signal generates a pulse to indicate that an indirect access to the internal key or statistics table of the encryption core is complete. Note that the pulse might be generated a few clock cycles after the deassertion of stat_rsvd_out_rx_top[121]. Bit [121]: This bit indicates the value of the rx_ind_axs_ctrl_ena field in the RX_INDIRECT_AXS_CTRL_REG register. This signal is asserted when an indirect register access to an encryption RAM is pending. You can monitor this signal instead of polling the rx_ind_axs_ctrl_ena field in the RX_INDIRECT_AXS_CTRL_REG register to determine when the indirect access transaction is complete. Bits [127:122]: Reserved |
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