| Port Name | Clock Domain | I/O | Description |
|---|---|---|---|
| enc_egr_axis_tdata<M>[127:0] | enc_egr_axis_clk | O | Encryption Egress AXI Segment <M> Data: Byte 0 of data on this segment is mapped to bits [7:0] and byte 15 is mapped to bits [127:120]. |
| enc_egr_axis_tid[5:0] | enc_egr_axis_clk | O | Encryption Egress Channel ID: This signal represents the channel ID of the data presented on encryption egress AXI4-Stream bus. This signal is valid only in the channelized mode. |
| enc_egr_axis_tuser_ena<M> | enc_egr_axis_clk | O | Per-segment enable. |
| enc_egr_axis_tuser_eop<M> | enc_egr_axis_clk | O | Segment End-of-Packet indicator: Only valid for enabled segments. |
| enc_egr_axis_tuser_err<M> | enc_egr_axis_clk | O | Egress Segment Error Indicator: This signal indicated that the packet ending on segment <M> had error indicator set when entered the core. |
| enc_egr_axis_tuser_mty<M>[3:0] | enc_egr_axis_clk | O | Segment Empty Bytes indicator: Only valid for enabled EOP segments. |
| enc_egr_axis_tuser_sop<M> | enc_egr_axis_clk | O | Segment Start-of-Packet indicator: Only valid for enabled segments. |
| enc_egr_axis_tvalid_<N> | enc_egr_axis_clk | O | Standard AXI Valid: This signal validates entire encryption egress AXI4-Stream bus for Port <N>. |
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