Entering CAVP Mode for a Port

Entering CAVP Mode for a Port - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID

PG372

Release Date

2024-01-30

Version

1.0 English

Set the port to be tested in the CAVP_TX_ENC_REQ_PORT_REG register.
Note: This must be consistent with how the HSC Subsystem is configured. For example, Port 2 cannot be selected if the HSC Subsystem is configured for a single port of 1x400G.
Set the appropriate c0_ctrl_tx_soft_flush through c3_ctrl_tx_soft_flush fields of the corresponding C0_CTL_TX_MAIN_REG through C3_CTL_TX_MAIN_REG registers to 1 for the selected port. This step is required to flush any context remaining in the memories from previous operations. It is important that no traffic is present on the selected port.
Set the cavp_tx_enc_req_en field in the CAVP_TX_ENC_REQ_MODE_REG register. It is important that step 1 is performed before this step because enabling CAVP mode will disconnect the selected port from the functional datapath and interrupt current activity. It is important that step 2 is done before this step to avoid issues when the mode changes to the mode specified by CAVP_TX_ENC_REQ_MODE_REG.
Set the appropriate c0_ctrl_tx_soft_flush through c3_ctrl_tx_soft_flush fields of the corresponding C0_CTL_TX_MAIN_REG through C3_CTL_TX_MAIN_REG registers to 0 for the selected port.
To start a test, see Executing a CAVP Test for a Port.