Example Design - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

This chapter explains the HSC Subsystem example design and various test scenarios implemented within the example design.

The HSC Subsystem example design demonstrates fixed speeds of 1x400GE Bulk Crypto, 2x200GE Bulk Crypto, 4x100GE Bulk Crypto, 1x400GE MACsec, 2x200GE MACsec, 4x100GE MACsec, 2x200GE IPsec, and 4x100GE IPsec simulations only.