Executing a CAVP Test for a Port - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)
Document ID
PG372
Release Date
2024-01-30
Version
1.0 English
Before commencing this procedure, you should have completed the procedure to enter CAVP mode.
  1. Set the mode and ensure the cavp_tx_enc_req_en bit remains set in CAVP_TX_ENC_REQ_MODE_REG.
  2. Set the various length fields in CAVP_TX_ENC_REQ_LEN_REG.
  3. Set various fields as follows. The order is not important.
    • CAVP_TX_ENC_REQ_KEY_REG_LSB, CAVP_TX_ENC_REQ_KEY_REG_MID1 through CAVP_TX_ENC_REQ_KEY_REG_MID6, CAVP_TX_ENC_REQ_KEY_REG_MSB7 to set the key.
    • CAVP_TX_ENC_REQ_IV_SALT_REG_LSB, CAVP_TX_ENC_REQ_IV_SALT_REG_MID1, and CAVP_TX_ENC_REQ_IV_SALT_REG_MSB2 for the IV/Salt.
    • The text is set in CAVP_TX_ENC_REQ_TXT_REG_<N>_LSB, CAVP_TX_ENC_REQ_TXT_REG_<N>_MID1, CAVP_TX_ENC_REQ_TXT_REG_<N>_MID2, CAVP_TX_ENC_REQ_TXT_REG_<N>_MSB3, (N=0,1, …, 9) registers.It is important that the lengths align with the values specified in CAVP_TX_ENC_REQ_LEN_REG.
    • In the Decryption case, the tag also needs to be set in CAVP_RX_DEC_REQ_TAG_REG_LSB, CAVP_RX_DEC_REQ_TAG_REG_MID1, CAVP_RX_DEC_REQ_TAG_REG_MID2, and CAVP_RX_DEC_REQ_TAG_REG_MSB3 registers.
  4. At this point, the test is ready to be started. Set the cavp_tx_enc_req_start bit (and optionally the cavp_tx_enc_req_pause bit) in the CAVP_TX_ENC_REQ_CTRL_REG.
    Note: Any transaction previously initiated with the pause bit set must end with an iteration where the pause bit is not set to terminate the transaction.
  5. If the pause bit was not asserted in the previous step, skip to the next step. If the pause bit was asserted:
    1. Poll the CAVP_TX_ENC_RESP_STAT_REG register to check the value of the cavp_tx_enc_resp_pend, cavp_tx_enc_resp_txt_valid, and cavp_tx_enc_resp_err bits. Successful completion of the current iteration is indicated by cavp_tx_enc_resp_pend == cavp_tx_enc_resp_txt_valid == 1 and cavp_tx_enc_resp_done == cavp_tx_enc_resp_resp_err == cavp_tx_enc_resp_config_err == 0. Assuming no errors and the cavp_tx_enc_resp_txt_valid bit is set, proceed to the next sub-step.
    2. Read the CAVP_TX_ENC_RESP_TXT_BCNT_REG register to determine how many valid bytes were captured on this iteration. It is possible that 0 bytes were captured.
    3. Read the number of bytes specified by CAVP_TX_ENC_RESP_TXT_BCNT_REG from the CAVP_TX_ENC_RESP_TXT_REG_<N>_LSB, CAVP_TX_ENC_RESP_TXT_REG_<N>_MID1, CAVP_TX_ENC_RESP_TXT_REG_<N>_MID2, and CAVP_TX_ENC_RESP_TXT_REG_<N>_MSB3 (N = 0, 1, …, 9) registers to gather the relevant information to generate the response file. This data will be overwritten on the next iteration, so it must be stored elsewhere.
    4. Clear the cavp_tx_enc_resp_txt_valid bit in the CAVP_TX_ENC_RESP_STAT_REG by writing 1 to it in preparation for the next iteration.
    5. In the CAVP_TX_ENC_REQ_LEN_REG register, set the cavp_tx_enc_req_aad_len fields to 0. Leave cavp_tx_enc_req_key_len unchanged. Set cavp_tx_enc_req_txt_len to the new value for the next iteration of the transaction.
    6. Set the CAVP_TX_ENC_REQ_TXT_REG_<N>_LSB, CAVP_TX_ENC_REQ_TXT_REG_<N>_MID1, CAVP_TX_ENC_REQ_TXT_REG_<N>_MID2, and CAVP_TX_ENC_REQ_TXT_REG_<N>_MSB3 (N = 0, 1, … 9) registers to the new text values. It is important that the lengths align with the values specified in the CAVP_TX_ENC_REQ_LEN_REG register.
    7. Return to step 4.
  6. Poll the CAVP_TX_ENC_RESP_STAT_REG register to check the value of cavp_tx_enc_resp_pend, cavp_tx_enc_resp_txt_valid and cavp_tx_enc_resp_err bits. Successful completion of the test is indicated by cavp_tx_enc_resp_done == cavp_tx_enc_resp_pend == 1, and cavp_tx_enc_resp_resp_err == cavp_tx_enc_resp_config_err == 0. Assuming no errors and the done bit is set, proceed to the next step.
  7. Read the CAVP_TX_ENC_RESP_TXT_BCNT_REG register to determine how many valid bytes were captured on this iteration.
  8. Read the number of bytes specified by CAVP_TX_ENC_RESP_TXT_BCNT_REG from the CAVP_TX_ENC_RESP_TXT_REG_<N>_LSB, CAVP_TX_ENC_RESP_TXT_REG_<N>_MID1, CAVP_TX_ENC_RESP_TXT_REG_<N>_MID2, CAVP_TX_ENC_RESP_TXT_REG_<N>_MSB3 (N = 0, 1, …, 9) and read the CAVP_TX_ENC_RESP_TAG_REG_<N>_LSB, CAVP_TX_ENC_RESP_TAG_REG_<N>_MID1, CAVP_TX_ENC_RESP_TAG_REG_<N>_MID2, CAVP_TX_ENC_RESP_TAG_REG_<N>_MSB3 (N = 0, 1, …, 9) registers (Encryption only) to gather the relevant information to generate the response file.
  9. Clear the bits in the CAVP_TX_ENC_RESP_STAT_REG register by writing 1 to them in preparation for the next test.
  10. From this point, the next test can be started from steps 1-4. If a new port is to be selected, or if returning to functional mode, refer to Exiting CAVP mode for a Port.
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