External Statistics Interfaces - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English
The HSC Subsystem presents all statistics increments through an external interface. The external statistics consist of two sets of statistics increments: Set A and Set B. These statistics are presented through two sets of pins identified by having "_a" and "_b" suffixes in their names.
  • SecY and SC stats in Set A are validated with signal tx/rx_stats_valid_a
  • SecY statistics in Set B are validated with signal tx/rx_secy_stats_valid_b
  • SC statistics in Set B are validated with signal tx/rx_sc_stats_valid_b
The output update order follows the SecY (Channel) calendar. In Channelized mode, the SecY order is user provided. In Fixed Port mode, the SecY order is the repeating strings of the enabled port numbers. For example:
  • In 4x100G mode, the SecY calendar order is the repeating strings of 0-1-2-3.
  • In 2x200G mode, the SecY calendar is the repeating strings of 0-2, and so on.
Any SecY or SC stat update may appear on either Set A or Set B interface as illustrated in the following figure. The user programmable logic may combine the information from the Set A signals and the Set B signals into a unified set of statistics information.
Figure 1. TX External Statistics Interface

The operation of the RX external statistics interface is shown in the following figure.

Figure 2. RX External Statistics Interface
Note: Byte count updates are provided in 512-byte increments, and the remainder at the end of packet is output coincident with the packet stats. Packet statistics updates occur after the core has detected the end of packet.