Features - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English
  • Supports 1 x 400 Gb/s, 2 x 200 Gb/s, 4 x 100 Gb/s, or any combination of 100 Gb/s and 200 Gb/s totaling up to 400 Gb/s
  • Supports 4 x 25 Gb/s, 4 x 10 Gb/s, 4 x 5 Gb/s, 4 x 2.5G, and 4 x 1Gb/s configurations for MACsec
  • Ingress-side and Egress-side AXI4-Stream interface at 390.625 Mhz nominal AXI4-Stream AXI4-Stream clock.
  • 40-channel 400 Gb/s Time-Sliced Encryption/Decryption Engine:
    • Channelized option for time-sliced applications
    • Up to 40 channels supported
    • User-defined bandwidth allocation granularity
  • Support for multiple protocols:
    • MACsec
    • IPsec
    • BulkCrypto
    • BulkECB (Electronic Code Book)