Memory Map - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

The AXI4-Lite interface enables access to the HSC Subsystem configuration, status, and statistics registers. The statistics are accessed using indirect register access.

Table 1. HSC Subsystem Memory Map
Base Address Region
0x0000 Revision Registers
0x0004 Configuration Registers
0x2000 Status Registers
0x3000 Encryption CAVP Configuration Registers
0x3400 Encryption CAVP Status Registers
0x3800 Decryption CAVP Configuration Registers
0x3C00 Decryption CAVP Status Registers
0x4800 Encryption Indirect Configuration Registers
0x4C00 Encryption Indirect Status Registers
0x6800 Decryption Indirect Configuration Registers
0x6C00 Decryption Indirect Status Registers
0x7000 Encryption Channelized Configuration Registers
0x7800 Decryption Channelized Configuration Registers