Operating Modes - 1.0 English

This section describes the various operating modes of the HSC Subsystem. The HSC Subsystem connects to user logic using Segmented AXI4-Stream interfaces. All Segmented AXI4-Stream interfaces use 128-bit segments.

In 4x100G mode, there are four independent Segmented AXI4-Stream user interfaces. Each 100G encryption/decryption port has a 256-bit Segmented AXI4-Stream interface (that is, two segments) on both the ingress and egress side. Similar AXI4-Stream user interfaces are used for low data rate configurations (that is, 4x25 Gb/s, 4x10 Gb/s, 4x5 Gb/s, 4x2.5 Gb/s, and 4x1 Gb/s).
In 1x200G and 2x100G mode, there are three independent Segmented AXI4-Stream user interfaces. Each 100G encryption/decryption port has a 256-bit Segmented AXI4-Stream interface (that is, two segments) on both the ingress and egress sides. The 200G encryption/decryption port has a 512-bit Segmented AXI4-Stream interface (that is, four segments) on the ingress and egress sides.
In 1x400G mode (Fixed Port or Channelized), there is one Segmented AXI4-Stream user interface. The 400G encryption/decryption port has a 1024-bit Segmented AXI4-Stream interface (that is, eight segments) on both the ingress and egress side.

The following table summarizes the operating modes of the HSC Subsystem and shows the bit mapping to AXI4-Stream interfaces. Note that Channelized mode is only available when the HSC Subsystem is operating with 1024-bit Segmented AXI4-Stream interface (that is, eight segments).

For operation with reduced clocks, the bandwidth of the core is proportionally reduced, as illustrated in the following table.

Note: There is no configuration difference when running with reduced clocks. Rather, for a given AXI4-Stream interface width, the bandwidth is proportionally reduced. For example, a 512-bit AXI4-Stream interface typically provides 200G capacity, but supports only 100G capacity when running with reduced clocks.

Table 1. Summary of HSC Subsystem Modes and AXI4-Stream Bit Mapping
AXI-S Instance	AXI-S Bit Mapping	Segment Number	HSC Subsystem Mode						AXI-S CLK (MHz)	CORE CLK (MHz)	Min Speed Grade
AXI-S Instance	AXI-S Bit Mapping	Segment Number	Fixed Port	Fixed Port	Fixed Port	Fixed Port	Fixed Port	Channelized	AXI-S CLK (MHz)	CORE CLK (MHz)	Min Speed Grade
3	[1023:768]	6,7	100G	100G	200G	200G	400G	400G	390.625 (typical) 409.4 (max)¹	781.25 (typical) 818.8 (max)¹	-2
2	[767:512]	4,5	100G	100G	200G	200G
1	[511:256]	2,3	100G	200G	100G	200G
0	[255:0]	0,1	100G	200G	100G	200G
3	[1023:768]	6,7	50G	50G	100G	100G	200G	200G	195.3125 (typical) 204.7 (max)	390.625 (typical) 409.4 (max)	-1
2	[767:512]	4,5	50G	50G	100G	100G
1	[511:256]	2,3	50G	100G	50G	100G
0	[255:0]	0,1	50G	100G	50G	100G
-2LP devices are limited to maximum of 400 MHz (800 MHz). -2MP and above support up to 409.4 MHz (818.8 MHz).

The HSC Subsystem also supports low data rate configurations for MACsec in Fixed Port mode with AXI4-Stream and core clocks running at lower frequencies than typical frequencies. The following table summarizes clock frequencies for MACsec low data rate configurations in Fixed Port mode.

Table 2. Summary of MACsec Low Data Rate Configurations
Fixed Port mode	AXI-S CLK (MHz)	Core CLK (MHz)	AXI4-Lite CLK (MHz)	Minimum value for AXI4-Lite timeout timer
4x1G	3.90625 (typical) 4.094 (max)	7.8125 (typical) 8.188 (max)	50 (min) 300 (max)	9
4x2.5G	9.765625 (typical) 10.235 (max)	19.53125(typical) 20.47 (max)	50 (min) 300 (max)	4
4x5G	19.53125 (typical) 20.47 (max)	39.0625 (typical) 40.94 (max)	50 (min) 300 (max)	2
4x10G	39.0625 (typical) 40.94 (max)	78.125 (typical) 81.88 (max)	50 (min) 300 (max)	0
4x25G	97.65625 (typical) 102.35 (max)	195.3125 (typical) 204.7 (max)	50 (min) 300 (max)	0

Note: For MACsec low data rate configurations, there are four independent Segmented AXI4-Stream user interfaces like the 4x100G Fixed Port mode. No other port configuration is supported. For each port, the bit mapping to AXI4-Stream interfaces is the same as the bit mapping in 4x100G mode as described in the previous table.