The following describes the receive (Decryption path) clocks in the HSC Subsystem.
- dec_core_clk
- This internal high-speed clock drives the bulk of the HSC Subsystem decryption datapath.
- dec_igr_axis_clk
- AXI4-Stream interface clock. The clock must operate a frequency high enough to maintain the desired data rate across the AXI4-Stream bus.
- dec_egr_axis_clk
- AXI4-Stream interface clock. The clock must operate a frequency high enough to maintain the desired data rate across the AXI4-Stream bus.
The HSC Subsystem requires the decryption AXI4-Stream interface clock and internal clock
frequencies to satisfy all of the following conditions:
- dec_core_clk
- 2 * dec_igr_axis_clk
- dec_igr_axis_clk
- dec_egr_axis