Reset Port Description - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID
PG372
Release Date
2024-01-30
Version
1.0 English

The below table list the HSC Subsystem reset pins along with the corresponding soft reset found in the GLOBAL_CONTROL_REG_RX or GLOBAL_CONTROL_REG_TX registers.

Table 1. Reset Port Description
HSC Subsystem Reset Pin Associated GLOBAL_CONTROL_REG_TX GLOBAL_CONTROL_REG_RX Bits Description
enc_igr_axis_reset soft_enc_igr_axis_reset Encryption Path Ingress AXI4-Stream reset
enc_egr_axis_reset soft_enc_egr_axis_reset Encryption Path Egress AXI4-Stream reset
enc_core_reset soft_enc_core_reset Encryption Path core reset
dec_igr_axis_reset soft_dec_igr_axis_reset Decryption Path Ingress AXI4-Stream reset
dec_egr_axis_reset soft_dec_egr_axis_reset Decryption Path Egress AXI4-Stream reset
dec_core_reset soft_dec_core_reset Decryption Path core reset
apb3_preset   Resets the AXI4-Lite port logic and status registers