The HSC Subsystem contains an internal statistics engine which monitors packet histogram statistics. The internal counters for the statistics are 64 bits wide and roll over when full.
Internal statistics counters are accessed using indirect register access. Transferring data from the internal statistics engine to the user register space takes a number of clock cycles. Completion of the update process is indicated by a register status bit. Refer to Statistics for more details on statistics definitions and how to access statistics in the HSC Subsystem.