In addition to status information that is available through AXI4-Lite registers, the HSC Subsystem IP provides status flag ports to enable ease of integration into user monitoring and interrupt logic. The following table has a list of the output status flags. All status ports are outputs.
| Port Name | Clock Domain | Description |
|---|---|---|
| stat_enc_ecc_correctable_err | enc_egr_axis_clk | Indication that a correctable ECC error has occurred |
| stat_enc_ecc_uncorrectable_err | enc_egr_axis_clk | Indication that an uncorrectable ECC error has occurred |
| stat_dec_ecc_correctable_err | dec_egr_axis_clk | Indication that a correctable ECC error has occurred |
| stat_dec_ecc_uncorrectable_err | dec_egr_axis_clk | Indication that an uncorrectable ECC error has occurred |