The following describes the transmit (Encryption path) clocks in the HSC Subsystem.
- enc_core_clk
- This internal high-speed clock drives the bulk of the HSC Subsystem encryption datapath.
- enc_igr_axis_clk
- AXI4-Stream interface clock. The clock must operate a frequency high enough to maintain the desired data rate across the AXI4-Stream bus.
- enc_egr_axis_clk
- AXI4-Stream interface clock. The clock must operate a frequency high enough to maintain the desired data rate across the AXI4-Stream bus.
The HSC Subsystem requires the encryption AXI4-Stream interface clock and
internal clock frequencies to satisfy all of the following conditions:
- enc_core_clk
- 2 * enc_igr_axis_clk
- enc_igr_axis_clk
- enc_egr_axis