User Interface - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)

Document ID

PG372

Release Date

2024-01-30

Version

1.0 English

An AXI4-Lite interface is used to configure the HSC Subsystem. Multiple APB3 interfaces for configuring the different generator and monitor modules are present in the example design.