Validate the Design on the VPK120 - 1.0 English

Versal Adaptive SoC Integrated 400G High Speed Channelized Cryptography Engine Subsystem Product Guide (PG372)
Document ID
PG372
Release Date
2024-01-30
Version
1.0 English
  1. After the bitstream (.pdi) and the application file (.elf) are ready, power ON the Versal Adaptive SoC board.

    Ensure that all power UART and loopback cable connections are properly connected.

  2. Launch the Vivado hardware manager. Select the Versal device and program the device.
    1. Launch the Vivado Lab Edition, and click Open Hardware Manager.
    2. Select Open Target > Open New Target > Next > Next > Finish.
    3. Right-click vjtag40_1, and select Program Device as shown in the following figure.
    4. Browse to the path where the bitstream (.pdi) is located, and then select Program.
  3. Open the xsdb console in C:\Xilinx\Vivado_Lab\2023.2\bin. Follow the procedure as shown in the following figure and observe the results in Tera Term.



    Note: Set the .elf file path before downloading .elf. See the results in Tera Term.