Word-based registers are concatenations of 4-byte registers to create a logical register of the required width (i.e., the word width). Examples include:
- CAVP_TX_ENC_REQ_IV_SALT_REG – 12-Bytes
- CAVP_ TX_ENC _REQ_IV_SALT_REG_LSB
- CAVP_ TX_ENC _REQ_IV_SALT_REG_MID1
- CAVP_ TX_ENC _REQ_IV_SALT_REG_MSB2
- CAVP_ TX_ENC _REQ_KEY_REG – 16/32-bytes
- CAVP_ TX_ENC _REQ_KEY_REG_LSB
- CAVP_ TX_ENC _REQ_KEY_REG_MID1
- CAVP_ TX_ENC _REQ_KEY_REG_MID2
- CAVP_ TX_ENC _REQ_KEY_REG_MID3
- CAVP_ TX_ENC _REQ_KEY_REG_MID4
- CAVP_ TX_ENC _REQ_KEY_REG_MID5
- CAVP_ TX_ENC _REQ_KEY_REG_MID6
- CAVP_ TX_ENC _REQ_KEY_REG_MSB7
- CAVP_TX_ENC_RESP_TAG_REG – 16-bytes
- CAVP_TX_ENC_RESP_TAG_REG_LSB
- CAVP_TX_ENC_RESP_TAG_REG_MID1
- CAVP_TX_ENC_RESP_TAG_REG_MID2
- CAVP_TX_ENC_RESP_TAG_REG_MSB3
- CAVP_RX_DEC_REQ_IV_SALT_REG – 12-Bytes
- CAVP_ RX_DEC _REQ_IV_SALT_REG_LSB
- CAVP_ RX_DEC _REQ_IV_SALT_REG_MID1
- CAVP_ RX_DEC _REQ_IV_SALT_REG_MSB2
- CAVP_ RX_DEC _REQ_KEY_REG – 16/32-bytes
- CAVP_ RX_DEC _REQ_KEY_REG_LSB
- CAVP_ RX_DEC _REQ_KEY_REG_MID1
- CAVP_ RX_DEC _REQ_KEY_REG_MID2
- CAVP_ RX_DEC _REQ_KEY_REG_MID3
- CAVP_ RX_DEC _REQ_KEY_REG_MID4
- CAVP_ RX_DEC _REQ_KEY_REG_MID5
- CAVP_ RX_DEC _REQ_KEY_REG_MID6
- CAVP_ RX_DEC _REQ_KEY_REG_MSB7
- CAVP_RX_DEC_REQ_TAG_REG – 16-bytes
- CAVP_RX_DEC_RESP_TAG_REG_LSB
- CAVP_RX_DEC_RESP_TAG_REG_MID1
- CAVP_RX_DEC_RESP_TAG_REG_MID2
- CAVP_RX_DEC_RESP_TAG_REG_MSB3
When accessing word-based registers, the values from the CAVP vectors can
be mapped directly to the word-based register for writes, and vice-versa for reads. The
CAVP values are assumed to be numbered [MSB:0], so bits
[31:0] are written to *_REG_LSB, bits [63:32] are written to *_REG_MID1 and so on. Similarly when
reading word-based registers, the read values are concatenated to match the CAVP format
as {*_REG_MSB,…,*_REG_MID1,*_REG_LSB}.
The following figure shows an example of writing the Key register for Encryption with a 256-bit key. If 128-bit keys are used, the upper bits can be omitted. Reading is the same, but in reverse.
