Auto-Pipeline Insertion - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

This mode is enabled by selecting Multi SLR Crossing for one or more AXI channels and checking the box Use timing-driven pipeline insertion in the configuration dialog. Like Multi SLR Crossing mode, this mode supports spanning zero or more SLR boundaries using a single AXI Register Slice instance. However, the number of pipeline stages inserted for both SLR-crossing and intra-SLR pipelining is determined automatically during the physical optimization stage of design implementation, as needed to satisfy pathway timing. No bubble cycles are incurred.

Note: Pipeline register resources and resulting latency might vary after each implementation run, and resulting latency will not be exhibited during behavioral simulation.

Auto-Pipeline Insertion mode drives registered payload outputs and registered VALID and READY handshake outputs as shown in the figure. The submodule instance names shown can be used in cell-name patterns when writing floorplanning (Pblock) constraints, as needed, to enforce proper SLR placement of source and destination submodules. (No intermediate SLRs need to be floorplanned.)

Figure 1. Auto-Pipeline Insertion AXI Register Slice Diagram