Constraining the Core - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

Required Constraints

When using the AXI Register Slice core in either the SLR Crossing, SLR TDM Crossing or Multi SLR Crossing mode, constraints can be applied to explicitly floorplan the SI-side and MI-side submodules of the core into the same SLRs as the connected master and slave endpoints. This will ensure that the SLR crossing(s) will take place between the intended flop-to-flop, unit-fanout, internal wires across all payload and handshake pathways within the core.

In most configurations, after synthesis, all logic and registers that should be placed into the master-side SLR (where the AXI master connected to the SI interface is located) will contain the cell name pattern *slr_master*. All logic and registers that should be placed into the slave-side SLR (where the AXI slave connected to the MI interface is located) will contain the cell name pattern *slr_slave*. When spanning three SLRs, all logic and registers that should be placed into the middle SLR will contain the cell name pattern *slr_middle*. Constraints that combine the instance name of the Register Slice and any of these submodule name patterns can then be used to group all cells in the core into their respective Pblocks for floorplanning.

For Auto-Pipeline Insertion mode, see the following figure for applicable submodule name patterns.

Figure 1. Auto-Pipeline Insertion Diagram

In the following example, an AXI Register Slice instance named my_reg is configured in Multi SLR Crossing mode (all channels) to cross two SLR boundaries that exist in the target device. One of the boundaries exists between row Y4 (the top of the lower SLR) and row Y5 (the bottom of the middle SLR). The other boundary exists between row Y9 (the top of the middle SLR) and row Y10 (the bottom of the upper SLR).

create_pblock lower_slr
add_cells_to_pblock [get_pblocks lower_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_master*"]
resize_pblock [get_pblocks lower_slr] -add SLR0
create_pblock center_slr
add_cells_to_pblock [get_pblocks center_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_middle*"]
resize_pblock [get_pblocks center_slr] -add SLR1
create_pblock upper_slr
add_cells_to_pblock [get_pblocks upper_slr] [get_cells -hierarchical -filter "NAME=~*my_reg*slr_slave*"]
resize_pblock [get_pblocks upper_slr] -add SLR2

Device, Package, and Speed Grade Selections

This section is not applicable for this IP core.

Clock Frequencies

This section is not applicable for this IP core.

Clock Management

This section is not applicable for this IP core.

Clock Placement

This section is not applicable for this IP core.

Banking

This section is not applicable for this IP core.

Transceiver Placement

This section is not applicable for this IP core.

I/O Standard and Placement

This section is not applicable for this IP core.