Customizing and Generating the Core - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

This section includes information about using Xilinx® tools to customize and generate the core in the Vivado® Design Suite.

If you are customizing and generating the core in the Vivado IP integrator, see the Vivado Design Suite User Guide: Designing IP Subsystems using IP Integrator (UG994) for detailed information. IP integrator might auto-compute certain configuration values when validating or generating the design. To check whether the values do change, see the description of the parameter in this chapter. To view the parameter value, run the validate_bd_design command in the Tcl console.

You can customize the IP for use in your design by specifying values for the various parameters associated with the IP core using the following steps:

  1. Select the IP from the IP catalog.
  2. Double-click the selected IP or select the Customize IP command from the toolbar or right-click menu.

For parameters showing an Auto/Manual selector widget to the left, values are normally filled in automatically according to the characteristics of connected endpoint IP when you Validate your BD design. By changing the widget to Manual, you can override the parameter value which, in turn, can override corresponding characteristics of the connected endpoint IP or interconnect IP, after you Validate your BD design.

For details, see the Vivado Design Suite User Guide: Designing with IP (UG896) and the Vivado Design Suite User Guide: Getting Started (UG910).

Figures in this chapter are illustrations of the Vivado IDE. The layout depicted here might vary from the current version.