Example Design - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

The AXI Register Slice core can generate an example design demonstrating its basic functionality when connected to a simple AXI master (traffic generator) and AXI slave. The example design system is customized to match the configuration settings you apply to the IP core. A test bench is provided to simulate the example design. The example design can also be implemented and analyzed using Vivado® Design Suite debug feature.