Features - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
Release Date
2.1 English
  • Individually configurable for each of the five AXI channels.
  • Facilitates timing closure by trading-off frequency versus latency.
  • One latency cycle per register-slice by default.
  • Able to propagate AXI traffic with no loss in data throughput (without bubble cycles) under all AXI handshake conditions.
  • Optional pipelining to cross Super Logic Region (SLR) in Stacked Silicon Interconnect (SSI) devices. See Large FPGA Methodology Guide: Including Stacked Silicon Interconnect (SSI) Technology (UG872) for more information.