Global Port Signals - 2.1 English

AXI Register Slice LogiCORE IP Product Guide (PG373)

Document ID
PG373
Release Date
2020-12-04
Version
2.1 English
Revision

The following table lists the global port signals for the core.

Table 1. Global Port Signals
Signal Name I/O Default Width Description (Range)
aclk I REQ 1 Clock input.
aresetn I REQ 1 Global Reset (active-Low).
aclk2x I REQ 1 This auxiliary clock input is only enabled when one or more AXI channels are configured in SLR TDM Crossing mode. The input must be exactly twice the frequency of aclk and should be generated from the same clock source with zero phase shift.